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path: root/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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* Zap unnecessary isIntDivCheap() check. PR11485. No testcase because this ↵Eli Friedman2011-12-071-1/+1
| | | | | | doesn't affect any in-tree target. llvm-svn: 146015
* Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves ↵Eli Friedman2011-12-071-13/+17
| | | | | | correctly. PR11494. llvm-svn: 145996
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-30/+49
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Revert r145273 and fix in SelectionDAG::InferPtrAlignment() instead.Evan Cheng2011-11-281-26/+12
| | | | | | | | | | | Conservatively returns zero when the GV does not specify an alignment nor is it initialized. Previously it returns ABI alignment for type of the GV. However, if the type is a "packed" type, then the under-specified alignments is attached to the load / store instructions. In that case, the alignment of the type cannot be trusted. rdar://10464621 llvm-svn: 145300
* DAG combine should not increase alignment of loads / stores with alignment lessEvan Cheng2011-11-281-12/+26
| | | | | | | | | than ABI alignment. These are loads / stores from / to "packed" data structures. Their alignments are intentionally under-specified. rdar://10301431 llvm-svn: 145273
* Make sure to replace the chain properly when DAGCombining a ↵Eli Friedman2011-11-161-4/+17
| | | | | | LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393. llvm-svn: 144863
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-151-1/+0
| | | | llvm-svn: 144634
* Don't try to form pre/post-indexed loads/stores until after LegalizeDAG ↵Eli Friedman2011-11-121-7/+7
| | | | | | runs. Fixes PR11029. llvm-svn: 144438
* Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.Lang Hames2011-11-081-0/+10
| | | | | | | | Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. llvm-svn: 144102
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-081-9/+11
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV()Richard Osborne2011-11-071-2/+2
| | | | | | and TargetLowering::BuildUDIV(). Fixes PR11283 llvm-svn: 143964
* Cleanup. Document. Make sure that this build_vector optimization only runs ↵Nadav Rotem2011-10-311-16/+29
| | | | | | before the op legalizer and that the used type is legal. llvm-svn: 143358
* Silence compiler warning.Benjamin Kramer2011-10-301-4/+4
| | | | llvm-svn: 143308
* Add a new DAGCombine optimization for BUILD_VECTOR.Nadav Rotem2011-10-291-0/+83
| | | | | | | If all of the inputs are zero/any_extended, create a new simple BV which can be further optimized by other BV optimizations. llvm-svn: 143297
* Don't crash on 128-bit sdiv by constant. Found by inspection.Eli Friedman2011-10-271-9/+6
| | | | llvm-svn: 143095
* Remove a couple redundant checks.Eli Friedman2011-10-251-2/+0
| | | | llvm-svn: 142959
* Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.Bob Wilson2011-10-181-2/+13
| | | | | | | | | svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands with illegal types, even before type legalization. For this testcase, that led to one BUILD_VECTOR with i16 operands and another with promoted i32 operands, which triggered the assertion. llvm-svn: 142370
* Fix SimplifySelectCC to add newly created nodes to the DAGCombinerDan Gohman2011-09-221-0/+3
| | | | | | worklist, as it may be possible to perform further optimization on them. llvm-svn: 140349
* Add a DAGCombine for subvector extracts to remove useless chains ofBruno Cardoso Lopes2011-09-201-0/+32
| | | | | | | subvector inserts and extracts. Initial patch by Rackover, Zvi with some tweak done by me. llvm-svn: 140204
* Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the ↵Eli Friedman2011-09-091-23/+32
| | | | | | same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. llvm-svn: 139407
* Add codegen support for vector select (in the IR this means a selectDuncan Sands2011-09-061-8/+9
| | | | | | | | | | | | with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
* Roll back the rest of r126557. It's a hack that will break in some obscure ↵Benjamin Kramer2011-08-191-6/+0
| | | | | | cases. llvm-svn: 138130
* Revert r137310 because it does not optimize any code on ToTNadav Rotem2011-08-121-32/+0
| | | | llvm-svn: 137466
* [AVX] When joining two XMM registers into a YMM register, make sure that theNadav Rotem2011-08-111-0/+32
| | | | | | | lower XMM register gets in first. This will allow the SUBREG pattern to elliminate the first vector insertion. llvm-svn: 137310
* Make sure this DAGCombine actually returns an UNDEF of the correct type; ↵Eli Friedman2011-07-251-1/+1
| | | | | | PR10476. llvm-svn: 135993
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-181-3/+3
| | | | llvm-svn: 135375
* Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-AEric Christopher2011-07-141-2/+10
| | | | | | Fixes rdar://9761830 llvm-svn: 135123
* Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. TheLang Hames2011-07-071-1/+6
| | | | | | | | | | | | | | | | hasPredecessorHelper function allows predecessors to be cached to speed up repeated invocations. This fixes PR10186. X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X) Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with empty Visited and Worklist sets (i.e. no caching over invocations). Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited and Worklist to speed up repeated calls. The Visited set is searched for X before going to the worklist to further search the DAG if necessary. llvm-svn: 134592
* Revert a part of r126557 which could create unschedulable DAGs.Benjamin Kramer2011-06-291-32/+0
| | | | llvm-svn: 134067
* Replace the existing forms of ConstantArray::get() with a single formJay Foad2011-06-221-1/+1
| | | | | | that takes an ArrayRef. llvm-svn: 133615
* Teach dag combine to match halfword byteswap patterns.Evan Cheng2011-06-211-2/+264
| | | | | | | | | | | | | | 1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 llvm-svn: 133503
* Add a DAGCombine for (ext (binop (load x), cst)).Nick Lewycky2011-06-161-61/+109
| | | | llvm-svn: 133124
* Enable the simplification of truncating-store after fixing the usage ofNadav Rotem2011-06-151-3/+4
| | | | | | | | GetDemandBits (which must operate on the vector element type). Fix the a usage of getZeroExtendInReg which must also be done on scalar types. llvm-svn: 133052
* When pattern matching during instruction selection make sure shl x,1 is notChad Rosier2011-06-141-0/+3
| | | | | | | | converted to add x,x if x is a undef. add undef, undef does not guarantee that the resulting low order bit is zero. Fixes <rdar://problem/9453156> and <rdar://problem/9487392>. llvm-svn: 133022
* Disable trunc-store simplification on vectors.Nadav Rotem2011-06-141-1/+1
| | | | llvm-svn: 132984
* Change this DAGCombine to build AND of SHR instead of SHR of AND; this ↵Eli Friedman2011-06-091-15/+16
| | | | | | | | matches the ordering we prefer in instcombine. Part of rdar://9562809. The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now. llvm-svn: 132809
* Revert 121907 (it causes llc crash) and apply original patch from PR9817.Devang Patel2011-05-231-0/+3
| | | | llvm-svn: 131926
* Implement mulo x, 2 -> addo x, x in DAGCombiner.Benjamin Kramer2011-05-211-0/+24
| | | | llvm-svn: 131800
* Misc. code cleanups.Dan Gohman2011-05-171-33/+34
| | | | llvm-svn: 131495
* Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain).Nadav Rotem2011-05-111-1/+1
| | | | | | | | If there is a store after the load node, then there is a chain, which means that there is another user. Thus, asking hasOneUser would fail. Instead we ask hasNUsesOfValue on the 'data' value. llvm-svn: 131183
* Indent properly, no functionality change.Duncan Sands2011-05-091-12/+12
| | | | llvm-svn: 131082
* PR9055: extend the fix to PR4050 (r70179) to apply to zext and anyext.Eli Friedman2011-04-161-2/+2
| | | | | | | Returning a new node makes the code try to replace the old node, which in the included testcase is killed by CSE. llvm-svn: 129650
* Fix another instance of the DAG combiner not using the correct type for the ↵Owen Anderson2011-04-141-3/+5
| | | | | | RHS of a shift. llvm-svn: 129522
* have dag combine zap "store undef", which can be formed during call loweringChris Lattner2011-04-091-2/+8
| | | | | | with undef arguments. llvm-svn: 129185
* Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich2011-04-021-0/+4
| | | | | | | | transformations in target-specific DAG combines without causing DAGCombiner to delete the same node twice. If you know of a better way to avoid this (see my next patch for an example), please let me know. llvm-svn: 128758
* Avoid replacing the value of a directly stored load with the stored value if ↵Evan Cheng2011-03-111-2/+1
| | | | | | the load is indexed. rdar://9117613. llvm-svn: 127440
* Can't introduce floating-point immediate constants after legalization.Stuart Hastings2011-03-021-2/+6
| | | | | | Radar 9056407. llvm-svn: 126864
* Fix typos in the comments.Nadav Rotem2011-02-271-4/+7
| | | | llvm-svn: 126565
* Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize ↵Benjamin Kramer2011-02-261-0/+38
| | | | | | | | | | | legalized code for large integer arithmetic. 1. Inform users of ADDEs with two 0 operands that it never sets carry 2. Fold other ADDs or ADDCs into the ADDE if possible It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code. llvm-svn: 126557
* Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson2011-02-251-48/+54
| | | | | | the type of the LHS. llvm-svn: 126518
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