summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Use reserve.Dan Gohman2008-06-301-0/+1
| | | | | | | | | | SelectionDAG::allnodes_size is linear, but that doesn't appear to outweigh the benefit of reducing heap traffic. If it does become a problem, we should teach SelectionDAG to keep a count of how many nodes are live, because there are several other places where that information would be useful as well. llvm-svn: 52926
* When folding a bitcast into a load or store, preserve the alignmentDan Gohman2008-06-281-2/+2
| | | | | | | information of the original load or store, which is checked to be at least as good, and possibly better. llvm-svn: 52849
* duncan points out that isOperationLegal includes a check forChris Lattner2008-06-261-2/+2
| | | | | | type legality. Thanks Duncan! llvm-svn: 52786
* when we know the signbit of an input to uint_to_fp is zero,Chris Lattner2008-06-261-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | change it to sint_to_fp on targets where that is cheaper (and visaversa of course). This allows us to compile uint_to_fp to: _test: movl 4(%esp), %eax shrl $23, %eax cvtsi2ss %eax, %xmm0 movl 8(%esp), %eax movss %xmm0, (%eax) ret instead of: .align 3 LCPI1_0: ## double .long 0 ## double least significant word 4.5036e+15 .long 1127219200 ## double most significant word 4.5036e+15 .text .align 4,0x90 .globl _test _test: subl $12, %esp movl 16(%esp), %eax shrl $23, %eax movl %eax, (%esp) movl $1127219200, 4(%esp) movsd (%esp), %xmm0 subsd LCPI1_0, %xmm0 cvtsd2ss %xmm0, %xmm0 movl 20(%esp), %eax movss %xmm0, (%eax) addl $12, %esp ret llvm-svn: 52747
* Duncan pointed out this code could be tidied.Dan Gohman2008-06-231-6/+3
| | | | llvm-svn: 52624
* Simplify some getNode calls.Dan Gohman2008-06-211-6/+3
| | | | llvm-svn: 52604
* Allow these transforms for types like i256 whileDuncan Sands2008-06-161-8/+6
| | | | | | | | still excluding types like i1 (not byte sized) and i120 (loading an i120 requires loading an i64, an i32, an i16 and an i8, which is expensive). llvm-svn: 52310
* The transforms in visitEXTRACT_VECTOR_ELT areDuncan Sands2008-06-151-4/+4
| | | | | | | | not valid if the load is volatile. Hopefully all wrong DAG combiner transforms of volatile loads and stores have now been caught. llvm-svn: 52293
* Remove a redundant AfterLegalize check. TurnDuncan Sands2008-06-141-4/+5
| | | | | | | | on some code when !AfterLegalize - but since this whole code section is turned off by an "if (0)" it's not really turning anything on. llvm-svn: 52276
* Disable some DAG combiner optimizations that may beDuncan Sands2008-06-131-58/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | wrong for volatile loads and stores. In fact this is almost all of them! There are three types of problems: (1) it is wrong to change the width of a volatile memory access. These may be used to do memory mapped i/o, in which case a load can have an effect even if the result is not used. Consider loading an i32 but only using the lower 8 bits. It is wrong to change this into a load of an i8, because you are no longer tickling the other three bytes. It is also unwise to make a load/store wider. For example, changing an i16 load into an i32 load is wrong no matter how aligned things are, since the fact of loading an additional 2 bytes can have i/o side-effects. (2) it is wrong to change the number of volatile load/stores: they may be counted by the hardware. (3) it is wrong to change a volatile load/store that requires one memory access into one that requires several. For example on x86-32, you can store a double in one processor operation, but to store an i64 requires two (two i32 stores). In a multi-threaded program you may want to bitcast an i64 to a double and store as a double because that will occur atomically, and be indivisible to other threads. So it would be wrong to convert the store-of-double into a store of an i64, because this will become two i32 stores - no longer atomic. My policy here is to say that the number of processor operations for an illegal operation is undefined. So it is alright to change a store of an i64 (requires at least two stores; but could be validly lowered to memcpy for example) into a store of double (one processor op). In short, if the new store is legal and has the same size then I say that the transform is ok. It would also be possible to say that transforms are always ok if before they were illegal, whether after they are illegal or not, but that's more awkward to do and I doubt it buys us anything much. However this exposed an interesting thing - on x86-32 a store of i64 is considered legal! That is because operations are marked legal by default, regardless of whether the type is legal or not. In some ways this is clever: before type legalization this means that operations on illegal types are considered legal; after type legalization there are no illegal types so now operations are only legal if they really are. But I consider this to be too cunning for mere mortals. Better to do things explicitly by testing AfterLegalize. So I have changed things so that operations with illegal types are considered illegal - indeed they can never map to a machine operation. However this means that the DAG combiner is more conservative because before it was "accidentally" performing transforms where the type was illegal because the operation was nonetheless marked legal. So in a few such places I added a check on AfterLegalize, which I suppose was actually just forgotten before. This causes the DAG combiner to do slightly more than it used to, which resulted in the X86 backend blowing up because it got a slightly surprising node it wasn't expecting, so I tweaked it. llvm-svn: 52254
* Sometimes (rarely) nodes held in LegalizeTypesDuncan Sands2008-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | maps can be deleted. This happens when RAUW replaces a node N with another equivalent node E, deleting the first node. Solve this by adding (N, E) to ReplacedNodes, which is already used to remap nodes to replacements. This means that deleted nodes are being allowed in maps, which can be delicate: the memory may be reused for a new node which might get confused with the old deleted node pointer hanging around in the maps, so detect this and flush out maps if it occurs (ExpungeNode). The expunging operation is expensive, however it never occurs during a llvm-gcc bootstrap or anywhere in the nightly testsuite. It occurs three times in "make check": Alpha/illegal-element-type.ll, PowerPC/illegal-element-type.ll and X86/mmx-shift.ll. If expunging proves to be too expensive then there are other more complicated ways of solving the problem. In the normal case this patch adds the overhead of a few more map lookups, which is hopefully negligable. llvm-svn: 52214
* Various tweaks related to apint codegen. No functionalityDuncan Sands2008-06-091-2/+2
| | | | | | change for non-funky-sized integers. llvm-svn: 52151
* Remove some DAG combiner assumptions about sizesDuncan Sands2008-06-091-28/+21
| | | | | | | | | | | of integer types. Fix the isMask APInt method to actually work (hopefully) rather than crashing because it adds apints of different bitwidths. It looks like isShiftedMask is also broken, but I'm leaving that one to the APInt people (it is not used anywhere). llvm-svn: 52142
* Remove comparison methods for MVT. The main causeDuncan Sands2008-06-081-23/+21
| | | | | | | | | | | of apint codegen failure is the DAG combiner doing the wrong thing because it was comparing MVT's using < rather than comparing the number of bits. Removing the < method makes this mistake impossible to commit. Instead, add helper methods for comparing bits and use them. llvm-svn: 52098
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-232/+232
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Add #includes to make some dependencies explicit.Dan Gohman2008-05-231-0/+1
| | | | llvm-svn: 51496
* Code simplification.Dan Gohman2008-05-201-6/+4
| | | | llvm-svn: 51345
* Instead of a vector load, shuffle and then extract an element. Load the ↵Evan Cheng2008-05-131-33/+66
| | | | | | | | | | | element from address with an offset. pshufd $1, (%rdi), %xmm0 movd %xmm0, %eax => movl 4(%rdi), %eax llvm-svn: 51026
* Xform bitconvert(build_pair(load a, load b)) to a single load if the load ↵Evan Cheng2008-05-121-0/+49
| | | | | | locations are at the right offset from each other. llvm-svn: 51008
* Evan pointed out that folding sext to zext may not be correctDan Gohman2008-04-281-1/+2
| | | | | | if the zext is not legal. llvm-svn: 50368
* Teach DAGCombine to convert (sext x) to (zext x) when theDan Gohman2008-04-281-0/+4
| | | | | | sign-bit of x is known to be zero. llvm-svn: 50357
* Ongoing work on improving the instruction selection infrastructure:Roman Levenstein2008-04-161-1/+2
| | | | | | | | | | Rename SDOperandImpl back to SDOperand. Introduce the SDUse class that represents a use of the SDNode referred by an SDOperand. Now it is more similar to Use/Value classes. Patch is approved by Dan Gohman. llvm-svn: 49795
* Re-commit of the r48822, where the infinite looping problem discoveredRoman Levenstein2008-04-071-8/+8
| | | | | | by Dan Gohman is fixed. llvm-svn: 49330
* Backing out 48222 temporarily.Evan Cheng2008-04-031-8/+8
| | | | llvm-svn: 49124
* Fix a DAGCombiner optimization to respect volatile qualification.Dan Gohman2008-03-311-1/+2
| | | | llvm-svn: 48994
* Use a linked data structure for the uses lists of an SDNode, just like Roman Levenstein2008-03-261-8/+8
| | | | | | | | | | | | | LLVM Value/Use does and MachineRegisterInfo/MachineOperand does. This allows constant time for all uses list maintenance operations. The idea was suggested by Chris. Reviewed by Evan and Dan. Patch is tested and approved by Dan. On normal use-cases compilation speed is not affected. On very big basic blocks there are compilation speedups in the range of 15-20% or even better. llvm-svn: 48822
* Handle a special case xor undef, undef -> 0. Technically this should be ↵Evan Cheng2008-03-251-0/+3
| | | | | | transformed to undef. But this is such a common idiom (misuse) we are going to handle it. llvm-svn: 48792
* Remove an unneeded test.Evan Cheng2008-03-241-1/+1
| | | | llvm-svn: 48755
* Teach DAG combiner to commute commutable binary nodes in order to achieve ↵Evan Cheng2008-03-221-0/+17
| | | | | | sdisel CSE. llvm-svn: 48673
* Check even more carefully before applying this DAGCombine transform.Christopher Lamb2008-03-201-13/+19
| | | | llvm-svn: 48580
* Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, ↵Evan Cheng2008-03-201-1/+3
| | | | | | result_size - n - m))) llvm-svn: 48578
* Fix X86's isTruncateFree to not claim that truncate to i1 is free. This ↵Christopher Lamb2008-03-191-0/+25
| | | | | | fixes Bill's testcase that failed for r48491. llvm-svn: 48542
* Temporarily revert r48491. It's breaking test/CodeGen/X86/xorl.ll.Bill Wendling2008-03-181-26/+0
| | | | llvm-svn: 48510
* Target independent DAG transform to use truncate for field extraction + sign ↵Christopher Lamb2008-03-181-0/+26
| | | | | | extend on targets where this is profitable. Passes nightly on x86-64. llvm-svn: 48491
* More APInt-ification.Dan Gohman2008-03-131-54/+64
| | | | llvm-svn: 48344
* Clean up my own mess.Evan Cheng2008-03-121-7/+1
| | | | | | X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases. llvm-svn: 48279
* Total brain cramp.Evan Cheng2008-03-121-1/+1
| | | | llvm-svn: 48274
* Somewhat better solution.Evan Cheng2008-03-101-3/+4
| | | | llvm-svn: 48170
* Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel2008-03-101-5/+5
| | | | | | | | return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
* DohEvan Cheng2008-03-101-1/+2
| | | | llvm-svn: 48140
* Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type ↵Evan Cheng2008-03-101-0/+4
| | | | | | (e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case. llvm-svn: 48136
* Rename isOperand() to isOperandOf() (and other similar methods). It always ↵Evan Cheng2008-03-041-9/+9
| | | | | | confuses me. llvm-svn: 47872
* Misc. APInt-ification in the DAGCombiner.Dan Gohman2008-03-031-17/+20
| | | | llvm-svn: 47869
* Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt.Dan Gohman2008-02-271-5/+12
| | | | | | | | Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
* Fix PR2096, a regression introduced with my patch last night. ThisChris Lattner2008-02-261-1/+1
| | | | | | also fixes cfrac, flops, and 175.vpr llvm-svn: 47605
* Fix isNegatibleForFree to not return true for ConstantFP nodes Chris Lattner2008-02-261-33/+47
| | | | | | | | | after legalize. Just because a constant is legal (e.g. 0.0 in SSE) doesn't mean that its negated value is legal (-0.0). We could make this stronger by checking to see if the negated constant is actually legal post negation, but it doesn't seem like a big deal. llvm-svn: 47591
* Convert MaskedValueIsZero and all its users to use APInt. Also addDan Gohman2008-02-251-28/+38
| | | | | | a SignBitIsZero function to simplify a common use case. llvm-svn: 47561
* Add explicit keywords.Dan Gohman2008-02-201-1/+1
| | | | llvm-svn: 47382
* Convert DAGCombiner to use the APInt form of ComputeMaskedBits.Dan Gohman2008-02-201-12/+13
| | | | llvm-svn: 47381
* Update gcc 4.3 warnings fix patch with recent head changesAnton Korobeynikov2008-02-201-8/+11
| | | | llvm-svn: 47368
OpenPOWER on IntegriCloud