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* Fix this harder.Chris Lattner2007-04-111-12/+19
| | | | llvm-svn: 35888
* don't create shifts by zero, fix some problems with my previous patchChris Lattner2007-04-111-3/+7
| | | | llvm-svn: 35887
* Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which oftenChris Lattner2007-04-111-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | allows other simplifications. For example, this compiles: int isnegative(unsigned int X) { return !(X < 2147483648U); } Into this code: x86: movl 4(%esp), %eax shrl $31, %eax ret arm: mov r0, r0, lsr #31 bx lr thumb: lsr r0, r0, #31 bx lr instead of: x86: cmpl $0, 4(%esp) sets %al movzbl %al, %eax ret arm: mov r3, #0 cmp r0, #0 movlt r3, #1 mov r0, r3 bx lr thumb: mov r2, #1 mov r1, #0 cmp r0, #0 blt LBB1_2 @entry LBB1_1: @entry cpy r2, r1 LBB1_2: @entry cpy r0, r2 bx lr Testcase here: test/CodeGen/Generic/ispositive.ll llvm-svn: 35883
* Codegen integer abs more efficiently using the trick from the PPC CWG. ThisChris Lattner2007-04-111-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll X86 Old: X86 New: _test: _test: movl 4(%esp), %ecx movl 4(%esp), %eax movl %ecx, %eax movl %eax, %ecx negl %eax sarl $31, %ecx testl %ecx, %ecx addl %ecx, %eax cmovns %ecx, %eax xorl %ecx, %eax ret ret PPC Old: PPC New: _test: _test: cmpwi cr0, r3, -1 srawi r2, r3, 31 neg r2, r3 add r3, r3, r2 bgt cr0, LBB1_2 ; xor r3, r3, r2 LBB1_1: ; blr mr r3, r2 LBB1_2: ; blr ARM Old: ARM New: _test: _test: rsb r3, r0, #0 add r3, r0, r0, asr #31 cmp r0, #0 eor r0, r3, r0, asr #31 movge r3, r0 bx lr mov r0, r3 bx lr Thumb Old: Thumb New: _test: _test: neg r2, r0 asr r2, r0, #31 cmp r0, #0 add r0, r0, r2 bge LBB1_2 eor r0, r2 LBB1_1: @ bx lr cpy r0, r2 LBB1_2: @ bx lr Sparc Old: Sparc New: test: test: save -96, %o6, %o6 save -96, %o6, %o6 sethi 0, %l0 sra %i0, 31, %l0 sub %l0, %i0, %l0 add %i0, %l0, %l1 subcc %i0, -1, %l1 xor %l1, %l0, %i0 bg .BB1_2 restore %g0, %g0, %g0 nop retl .BB1_1: nop or %g0, %l0, %i0 .BB1_2: restore %g0, %g0, %g0 retl nop It also helps alpha/ia64 :) llvm-svn: 35881
* 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.Scott Michel2007-04-021-22/+59
| | | | | | | | | 2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL patterns. This was motivated by the X86/rotate.ll testcase, which should now generate code for other platforms (and soon-to-come platforms.) Rewrote code slightly to make it easier to read. llvm-svn: 35605
* Fix incorrect combination of different loads. Reenable zext-over-truncateDale Johannesen2007-03-301-3/+1
| | | | | | combination. llvm-svn: 35517
* Disable load width reduction xform of variant (zext (truncate load x)) forEvan Cheng2007-03-291-1/+3
| | | | | | big endian targets until llvm-gcc build issue has been resolved. llvm-svn: 35449
* SIGN_EXTEND_INREG requires one extra operand, a ValueType node.Evan Cheng2007-03-261-2/+6
| | | | llvm-svn: 35350
* Adjust offset to compensate for big endian machines.Evan Cheng2007-03-241-7/+5
| | | | llvm-svn: 35293
* Make sure SEXTLOAD of the specific type is supported on the target.Evan Cheng2007-03-231-0/+4
| | | | llvm-svn: 35289
* Also replace uses of SRL if that's also folded during ReduceLoadWidth().Evan Cheng2007-03-231-1/+8
| | | | llvm-svn: 35286
* A couple of bug fixes for reducing load width xform:Evan Cheng2007-03-231-7/+16
| | | | | | | 1. Address offset is in bytes. 2. Make sure truncate node uses are replaced with new load. llvm-svn: 35274
* More opportunities to reduce load size.Evan Cheng2007-03-221-45/+101
| | | | llvm-svn: 35254
* fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))Evan Cheng2007-03-211-6/+24
| | | | llvm-svn: 35239
* Avoid combining indexed load further.Evan Cheng2007-03-071-8/+14
| | | | llvm-svn: 35005
* fold away addc nodes when we know there cannot be a carry-out.Chris Lattner2007-03-041-8/+27
| | | | llvm-svn: 34913
* generalizeChris Lattner2007-03-041-5/+9
| | | | llvm-svn: 34910
* canonicalize constants to the RHS of addc/adde. If nothing uses the carry ↵Chris Lattner2007-03-041-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | out of addc, turn it into add. This allows us to compile: long long test(long long A, unsigned B) { return (A + ((long long)B << 32)) & 123; } into: _test: movl $123, %eax andl 4(%esp), %eax xorl %edx, %edx ret instead of: _test: xorl %edx, %edx movl %edx, %eax addl 4(%esp), %eax ;; add of zero andl $123, %eax ret llvm-svn: 34909
* Fold (sext (truncate x)) more aggressively, by avoiding creation of aChris Lattner2007-02-261-10/+34
| | | | | | | | | sextinreg if not needed. This is useful in two cases: before legalize, it avoids creating a sextinreg that will be trivially removed. After legalize if the target doesn't support sextinreg, the trunc/sext would not have been removed before. llvm-svn: 34621
* Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer.Evan Cheng2007-02-081-399/+5
| | | | llvm-svn: 34065
* Fix for PR1108: type of insert_vector_elt index operand is PtrVT, not MVT::i32.Evan Cheng2007-01-201-3/+4
| | | | llvm-svn: 33398
* Remove this xform:Evan Cheng2007-01-191-7/+26
| | | | | | | | | | (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) Replace it with: (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) This fixes test/CodeGen/ARM/smul.ll llvm-svn: 33361
* Fix PR1114 and CodeGen/Generic/2007-01-15-LoadSelectCycle.ll by beingChris Lattner2007-01-161-25/+41
| | | | | | | careful when folding "c ? load p : load q" that C doesn't reach either load. If so, folding this into load (c ? p : q) will induce a cycle in the graph. llvm-svn: 33251
* add options to view the dags before the first or second pass of dag combine.Chris Lattner2007-01-161-0/+18
| | | | llvm-svn: 33249
* Implement some trivial FP foldings when -enable-unsafe-fp-math is specified.Chris Lattner2007-01-081-0/+15
| | | | | | This implements CodeGen/PowerPC/unsafe-math.ll llvm-svn: 33024
* Eliminate static ctors from StatisticsChris Lattner2006-12-191-8/+4
| | | | llvm-svn: 32698
* Cannot combine an indexed load / store any further.Evan Cheng2006-12-161-1/+10
| | | | llvm-svn: 32629
* This code was usurping the sextload expand in teh legalizer. Just makeJim Laskey2006-12-151-7/+9
| | | | | | sure the right conditions are checked. llvm-svn: 32611
* make this code more aggressive about turning store fpimm into store int imm.Chris Lattner2006-12-121-9/+32
| | | | | | This is not sufficient to fix X86/store-fp-constant.ll llvm-svn: 32465
* Don't convert store double C, Ptr to store long C, Ptr if i64 is not a legal ↵Evan Cheng2006-12-111-9/+12
| | | | | | type. llvm-svn: 32434
* Move something that should be in the dag combiner from the legalizer to theNate Begeman2006-12-111-0/+14
| | | | | | dag combiner. llvm-svn: 32431
* Fix CodeGen/PowerPC/2006-12-07-SelectCrash.ll on PPC64Chris Lattner2006-12-071-1/+4
| | | | llvm-svn: 32336
* Removing even more <iostream> includes.Bill Wendling2006-12-071-17/+15
| | | | llvm-svn: 32320
* Detemplatize the Statistic class. The only type it is instantiated withChris Lattner2006-12-061-3/+3
| | | | | | is 'unsigned'. llvm-svn: 32279
* For better or worse, load from i1 is assumed to be zero extended. Do notChris Lattner2006-11-271-1/+6
| | | | | | form a load from i1 from larger loads that may not be zext'd. llvm-svn: 31933
* Fix PR1011 and CodeGen/Generic/2006-11-20-DAGCombineCrash.llChris Lattner2006-11-201-2/+2
| | | | llvm-svn: 31878
* Fix an incorrectly inverted condition.Evan Cheng2006-11-161-1/+1
| | | | llvm-svn: 31773
* disallow preinc of a frameindex. This is not profitable and causes 2-addrChris Lattner2006-11-111-5/+11
| | | | | | pass to explode. This fixes a bunch of llc-beta failures on ppc last night. llvm-svn: 31661
* reduce indentation by using early exits. No functionality change.Chris Lattner2006-11-111-154/+161
| | | | llvm-svn: 31660
* move big chunks of code out-of-line, no functionality change.Chris Lattner2006-11-111-235/+241
| | | | llvm-svn: 31658
* Fix a dag combiner bug exposed by my recent instcombine patch. This fixesChris Lattner2006-11-101-1/+1
| | | | | | CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast llvm-svn: 31644
* When forming a pre-indexed store, make sure ptr isn't the same or is a pred ↵Evan Cheng2006-11-101-7/+16
| | | | | | of value being stored. It would cause a cycle. llvm-svn: 31631
* Don't attempt expensive pre-/post- indexed dag combine if target does not ↵Evan Cheng2006-11-091-1/+18
| | | | | | support them. llvm-svn: 31598
* Rename ISD::MemOpAddrMode to ISD::MemIndexedModeEvan Cheng2006-11-091-2/+2
| | | | llvm-svn: 31595
* getPostIndexedAddressParts change: passes in load/store instead of its ↵Evan Cheng2006-11-091-3/+1
| | | | | | loaded / stored VT. llvm-svn: 31584
* Match more post-indexed ops.Evan Cheng2006-11-081-2/+6
| | | | llvm-svn: 31569
* Remove redundant <cmath>.Jim Laskey2006-11-081-1/+0
| | | | llvm-svn: 31561
* - When performing pre-/post- indexed load/store transformation, do not worryEvan Cheng2006-11-081-90/+29
| | | | | | | | about whether the new base ptr would be live below the load/store. Let two address pass split it back to non-indexed ops. - Minor tweaks / fixes. llvm-svn: 31544
* Fixed a minor bug preventing some pre-indexed load / store transformation.Evan Cheng2006-11-081-3/+3
| | | | llvm-svn: 31543
* Fix a obscure post-indexed load / store dag combine bug.Evan Cheng2006-11-081-1/+1
| | | | llvm-svn: 31537
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