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path: root/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
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* Rewrite the SDep class, and simplify some of the related code.Dan Gohman2008-12-091-23/+24
| | | | | | | | | | | | | | | | | The Cost field is removed. It was only being used in a very limited way, to indicate when the scheduler should attempt to protect a live register, and it isn't really needed to do that. If we ever want the scheduler to start inserting copies in non-prohibitive situations, we'll have to rethink some things anyway. A Latency field is added. Instead of giving each node a single fixed latency, each edge can have its own latency. This will eventually be used to model various micro-architecture properties more accurately. The PointerIntPair class and an internal union are now used, which reduce the overall size. llvm-svn: 60806
* Fix the top-level comments, and fix some 80-column violations.Dan Gohman2008-12-081-7/+9
| | | | llvm-svn: 60707
* Add minimal support for disambiguating memory references. CurrentlyDan Gohman2008-12-041-13/+123
| | | | | | the main thing this covers is spills to distinct spill slots. llvm-svn: 60517
* Pass the isAntiDep argument.Dan Gohman2008-11-241-1/+1
| | | | llvm-svn: 59968
* Correctly set the isCtrl flag for chain dependencies.Dan Gohman2008-11-211-4/+4
| | | | llvm-svn: 59837
* Update comments.Dan Gohman2008-11-211-9/+9
| | | | llvm-svn: 59836
* Set the isAntiDep flag in the MachineInstr scheduler.Dan Gohman2008-11-211-1/+1
| | | | llvm-svn: 59787
* Use ComputeLatency in the MachineInstr scheduler.Dan Gohman2008-11-211-0/+3
| | | | llvm-svn: 59777
* Implement ComputeLatency for MachineInstr ScheduleDAGs. FactorDan Gohman2008-11-211-1/+10
| | | | | | | | some of the latency computation logic out of the SDNode ScheduleDAG code into a TargetInstrItineraries helper method to help with this. llvm-svn: 59761
* Treat mid-block labels the same as terminators when building theDan Gohman2008-11-201-1/+1
| | | | | | | | | | MachineInstr scheduling DAG, meaning they implicitly depend on all preceding defs. This fixes Benchmarks/Shootout-C++/except and Regression/C++/EH/simple_rethrow in -relocation-model=pic -disable-post-RA-scheduler=false mode. llvm-svn: 59747
* Experimental post-pass scheduling support. Post-pass schedulingDan Gohman2008-11-191-0/+135
is currently off by default, and can be enabled with -disable-post-RA-scheduler=false. This doesn't have a significant impact on most code yet because it doesn't yet do anything to address anti-dependencies and it doesn't attempt to disambiguate memory references. Also, several popular targets don't have pipeline descriptions yet. The majority of the changes here are splitting the SelectionDAG-specific code out of ScheduleDAG, so that ScheduleDAG can be moved to libLLVMCodeGen.a. The interface between ScheduleDAG-using code and the rest of the scheduling code is somewhat rough and will evolve. llvm-svn: 59676
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