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* Move Value::getUnderlyingObject to be a standaloneDan Gohman2010-12-151-2/+3
| | | | | | | function so that it can live in Analysis instead of VMCore. llvm-svn: 121885
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-031-3/+5
| | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 llvm-svn: 118135
* Putting r117193 back except for the compile time cost. Rather than assuming ↵Evan Cheng2010-10-271-3/+10
| | | | | | fallthroughs uses all registers, just gather the union of all successor liveins. llvm-svn: 117506
* Neuter r117193 as it causes significant post-ra scheduler compile time ↵Evan Cheng2010-10-251-2/+2
| | | | | | regression. llvm-svn: 117329
* Properly model the latency of register defs which are 1) function returns orEvan Cheng2010-10-231-16/+76
| | | | | | | | | | | 2) live-outs. Previously the post-RA schedulers completely ignore these dependencies since returns, branches, etc. are all scheduling barriers. This patch model the latencies between instructions being scheduled and the barriers. It also handle calls by marking their register uses. llvm-svn: 117193
* Avoid compiler warning: comparison between signed and unsigned integer.Evan Cheng2010-10-081-1/+1
| | | | llvm-svn: 116119
* Fix operand latency computation in cases where the definition operand isEvan Cheng2010-10-081-0/+11
| | | | | | | | | | implicit. e.g. %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def> %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ... The real definition indices are 0,1. llvm-svn: 116080
* Remove unused variables.Nick Lewycky2010-10-061-3/+0
| | | | llvm-svn: 115802
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-061-5/+4
| | | | | | | | | | | | | allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
* Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMPEvan Cheng2010-09-291-20/+17
| | | | | | pipeline forwarding path. llvm-svn: 115098
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-15/+14
| | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
* Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectorsBob Wilson2010-07-241-1/+2
| | | | | | | instead of fixed size arrays, so that increasing FirstVirtualRegister to 16K won't cause a compile time performance regression. llvm-svn: 109330
* Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.Bill Wendling2010-07-151-3/+3
| | | | llvm-svn: 108452
* Fix the post-RA instruction scheduler to handle instructions referenced byJim Grosbach2010-05-191-3/+3
| | | | | | more than one dbg_value instruction. rdar://7759363 llvm-svn: 104174
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-011-2/+1
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* Fix -Wcast-qual warnings.Dan Gohman2010-04-171-4/+4
| | | | llvm-svn: 101655
* Reduce indentation.Evan Cheng2010-03-221-35/+34
| | | | llvm-svn: 99214
* 80 col violation.Evan Cheng2010-03-221-1/+2
| | | | llvm-svn: 99195
* Progress towards shepherding debug info through SelectionDAG.Dale Johannesen2010-03-101-1/+45
| | | | | | | No functional effect yet. This is still evolving and should not be viewed as final. llvm-svn: 98195
* There are two ways of checking for a given type, for example isa<PointerType>(T)Duncan Sands2010-02-161-2/+2
| | | | | | | and T->isPointerTy(). Convert most instances of the first form to the second form. Requested by Chris. llvm-svn: 96344
* Fix dependencies added to model memory aliasing for post-RA scheduling. The ↵David Goodwin2009-11-091-96/+97
| | | | | | dependencies were overly conservative for memory access that are known not to alias. llvm-svn: 86580
* Correctly add chain dependencies around calls and unknown-side-effect ↵David Goodwin2009-11-051-2/+3
| | | | | | instructions. llvm-svn: 86080
* <rdar://problem/7352605>. When building schedule graph use mayAlias ↵David Goodwin2009-11-031-15/+43
| | | | | | information to avoid chaining loads/stores of spill slots with non-aliased memory ops. llvm-svn: 85934
* Chain dependencies used to enforce memory order should have latency of 0 ↵David Goodwin2009-11-021-14/+23
| | | | | | (except for true dependency of Store followed by aliased Load... we estimate that case with a single cycle of latency assuming the hardware will bypass) llvm-svn: 85807
* When checking whether a def of an aliased register is dead, ask theDan Gohman2009-10-261-1/+1
| | | | | | | | | | machineinstr whether the aliased register is dead, rather than the original register is dead. This allows it to get the correct answer when examining an instruction like this: CALLpcrel32 <ga:foo>, %AL<imp-def>, %EAX<imp-def,dead> where EAX is dead but a subregister of it is still live. This fixes PR5294. llvm-svn: 85135
* Spill slots cannot alias.Evan Cheng2009-10-181-5/+8
| | | | llvm-svn: 84432
* -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixedEvan Cheng2009-10-181-3/+12
| | | | | | | | | | | stack slots and giving them different PseudoSourceValue's did not fix the problem of post-alloc scheduling miscompiling llvm itself. - Apply Dan's conservative workaround by assuming any non fixed stack slots can alias other memory locations. This means a load from spill slot #1 cannot move above a store of spill slot #2. - Enable post-alloc scheduling for x86 at optimization leverl Default and above. llvm-svn: 84424
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-091-2/+2
| | | | | | | | | | | | | | is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. llvm-svn: 83687
* Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman2009-10-071-1/+1
| | | | | | | | | implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. llvm-svn: 83475
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-6/+7
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng2009-09-181-1/+2
| | | | | | | | sdisel will use to properly complete phi nodes. Not functionality change yet. llvm-svn: 82273
* Use the schedule itinerary operand use/def cycle information to adjust ↵David Goodwin2009-08-191-3/+60
| | | | | | dependence edge latency for post-RA scheduling. llvm-svn: 79425
* Add callback to allow target to adjust latency of schedule dependency edge.David Goodwin2009-08-131-5/+10
| | | | llvm-svn: 78910
* Post RA scheduler changes. Introduce a hazard recognizer that uses the ↵David Goodwin2009-08-101-7/+10
| | | | | | target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. llvm-svn: 78563
* Fix a typo in a comment.Dan Gohman2009-08-071-1/+1
| | | | llvm-svn: 78362
* Eliminate yet another copy of getOpcode.Dan Gohman2009-07-171-17/+6
| | | | llvm-svn: 76236
* Move isLCSSAForm, isLoopInvariant, getCanonicalInductionVariable,Dan Gohman2009-07-131-0/+1
| | | | | | | | and related functions out of LoopBase and into Loop, since they are specific to BasicBlock-based loops. This also allows the code to be moved out-of-line. llvm-svn: 75523
* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-111-3/+16
| | | | | | | | | | | instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. llvm-svn: 64288
* Factor out more code for computing register live-range informationforDan Gohman2009-02-101-120/+40
| | | | | | | | | | | scheduling, and generalize is so that preserves state across scheduling regions. This fixes incorrect live-range information around terminators and labels, which are effective region boundaries. In place of looking for terminators to anchor inter-block dependencies, introduce special entry and exit scheduling units for this purpose. llvm-svn: 64254
* Move ScheduleDAGInstrs.h to be a private header. Front-endsDan Gohman2009-02-061-1/+1
| | | | | | | | that used this header to select a scheduling policy should use SchedulerRegistry.h instead (llvm-gcc and clang were updated a while ago). llvm-svn: 63934
* Fix a post-RA scheduling dependency bug.Dan Gohman2009-01-301-11/+90
| | | | | | | | | | | | | | | If a MachineInstr doesn't have a memoperand but has an opcode that is known to load or store, assume its memory reference may alias *anything*, including stack slots which the compiler completely controls. To partially compensate for this, teach the ScheduleDAG building code to do basic getUnderlyingValue analysis. This greatly reduces the number of instructions that require restrictive dependencies. This code will need to be revisited when we start doing real alias analysis, but it should suffice for now. llvm-svn: 63370
* Instead of adding dependence edges between terminator instructionsDan Gohman2009-01-161-10/+34
| | | | | | | | | | | | | | and every other instruction in their blocks to keep the terminator instructions at the end, teach the post-RA scheduler how to operate on ranges of instructions, and exclude terminators from the range of instructions that get scheduled. Also, exclude mid-block labels, such as EH_LABEL instructions, and schedule code before them separately from code after them. This fixes problems with the post-RA scheduler moving code past EH_LABELs. llvm-svn: 62366
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-18/+21
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* Clean up the atomic opcodes in SelectionDAG.Dan Gohman2008-12-231-0/+1
| | | | | | | | | | | | | This removes all the _8, _16, _32, and _64 opcodes and replaces each group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode is now used to carry the size information. In tablegen, the size-specific opcodes are replaced by size-independent opcodes that utilize the ability to compose them with predicates. This shrinks the per-opcode tables and makes the code that handles atomics much more concise. llvm-svn: 61389
* Rename BuildSchedUnits to BuildSchedGraph, and refactor theDan Gohman2008-12-231-1/+1
| | | | | | code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions. llvm-svn: 61376
* Use isTerminator() instead of isBranch()||isReturn() inDan Gohman2008-12-231-3/+2
| | | | | | | | several places. isTerminator() returns true for a superset of cases, and includes things like FP_REG_KILL, which are nither return or branch but aren't safe to move/remat/etc. llvm-svn: 61373
* Add initial support for back-scheduling address computations,Dan Gohman2008-12-161-1/+132
| | | | | | | especially in the case of addresses computed from loop induction variables. llvm-svn: 61075
* Fix some register-alias-related bugs in the post-RA scheduler livenessDan Gohman2008-12-161-18/+50
| | | | | | | | | | | | | | computation code. Also, avoid adding output-depenency edges when both defs are dead, which frequently happens with EFLAGS defs. Compute Depth and Height lazily, and always in terms of edge latency values. For the schedulers that don't care about latency, edge latencies are set to 1. Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array. These are all subsumed by the Depth and Height fields. llvm-svn: 61073
* Add a simple target-independent heuristic to allow targets with noDan Gohman2008-12-161-0/+6
| | | | | | instruction itinerary data to back-schedule loads. llvm-svn: 61070
* Rewrite the SDep class, and simplify some of the related code.Dan Gohman2008-12-091-23/+24
| | | | | | | | | | | | | | | | | The Cost field is removed. It was only being used in a very limited way, to indicate when the scheduler should attempt to protect a live register, and it isn't really needed to do that. If we ever want the scheduler to start inserting copies in non-prohibitive situations, we'll have to rethink some things anyway. A Latency field is added. Instead of giving each node a single fixed latency, each edge can have its own latency. This will eventually be used to model various micro-architecture properties more accurately. The PointerIntPair class and an internal union are now used, which reduce the overall size. llvm-svn: 60806
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