| Commit message (Collapse) | Author | Age | Files | Lines |
... | |
|
|
|
|
|
|
|
| |
liveintervalanalysis and coalescer handling of implicit_def.
Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.
llvm-svn: 74601
|
|
|
|
|
|
| |
the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
llvm-svn: 74580
|
|
|
|
|
|
| |
isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.).
llvm-svn: 74519
|
|
|
|
|
|
|
|
|
|
| |
operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.
This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.
llvm-svn: 74518
|
|
|
|
|
|
| |
live range may overlap another def of same register.
llvm-svn: 73255
|
|
|
|
|
|
|
|
|
|
|
|
| |
register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).
llvm-svn: 68714
|
|
|
|
| |
llvm-svn: 61715
|
|
|
|
| |
llvm-svn: 61390
|
|
|
|
|
|
| |
data from a previous block.
llvm-svn: 61237
|
|
|
|
| |
llvm-svn: 60434
|
|
|
|
|
|
|
|
|
| |
the first use of a register after a given machine instruction.
- When scavenging a register, in addition to the spill, insert a restore before the first use.
- Abort if client is looking to scavenge a register even when a previously scavenged register is still live.
llvm-svn: 59697
|
|
|
|
| |
llvm-svn: 59566
|
|
|
|
| |
llvm-svn: 59562
|
|
|
|
|
|
| |
clobber def should not interfere with a normal def which happens one slot later.
llvm-svn: 59559
|
|
|
|
|
|
| |
isReg, etc., from isRegister, etc.
llvm-svn: 57006
|
|
|
|
| |
llvm-svn: 53196
|
|
|
|
| |
llvm-svn: 51591
|
|
|
|
| |
llvm-svn: 49512
|
|
|
|
|
|
|
| |
2. Coalescer can now create an interesting situation where a register def can
reaches itself without being killed.
llvm-svn: 49246
|
|
|
|
|
|
| |
kills the sub-register.
llvm-svn: 48038
|
|
|
|
|
|
| |
register, there must be an implicit def of the super-register on the MI.
llvm-svn: 48024
|
|
|
|
|
|
|
|
| |
%r3<def> = OR %x3<kill>, %x3
We don't want to mark the %r3 as unused even though it's a sub-register of %x3.
llvm-svn: 48003
|
|
|
|
|
|
| |
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
llvm-svn: 47927
|
|
|
|
|
|
| |
registers.
llvm-svn: 47861
|
|
|
|
| |
llvm-svn: 47200
|
|
|
|
| |
llvm-svn: 46930
|
|
|
|
|
|
|
| |
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
llvm-svn: 45695
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
llvm-svn: 45674
|
|
|
|
| |
llvm-svn: 45484
|
|
|
|
| |
llvm-svn: 45418
|
|
|
|
|
|
| |
the stored register is killed.
llvm-svn: 44600
|
|
|
|
|
|
|
| |
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
llvm-svn: 41958
|
|
|
|
| |
llvm-svn: 37890
|
|
|
|
|
|
| |
eliminateFrameIndex() must adjust SP offset with size of call frames.
llvm-svn: 36625
|
|
|
|
| |
llvm-svn: 36483
|
|
|
|
| |
llvm-svn: 35618
|
|
|
|
|
|
| |
hopefully forestall similar errors.
llvm-svn: 35362
|
|
|
|
| |
llvm-svn: 35226
|
|
|
|
| |
llvm-svn: 34985
|
|
|
|
|
|
| |
use of furthest away to make it available.
llvm-svn: 34964
|
|
|
|
| |
llvm-svn: 34844
|
|
|
|
|
|
| |
registers.
llvm-svn: 34784
|
|
|
|
| |
llvm-svn: 34770
|
|
|
|
| |
llvm-svn: 34700
|
|
|
|
| |
llvm-svn: 34698
|
|
|
|
| |
llvm-svn: 34690
|
|
|
|
|
|
| |
instruction between now and next forward() call.
llvm-svn: 34649
|
|
|
|
| |
llvm-svn: 34596
|
|
|
|
| |
llvm-svn: 34525
|
|
tracking live registers per MBB.
llvm-svn: 34511
|