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* Fix target-customized spilling in the register scavengerHal Finkel2013-03-271-1/+1
| | | | | | | | | | | | This is a follow-up to r178073 (which should actually make target-customized spilling work again). I still don't have a regression test for this (but it would be good to have one; Thumb 1 and Mips16 use this callback as well). Patch by Richard Sandiford. llvm-svn: 178137
* Fix the register scavenger for targets that provide custom spillingHal Finkel2013-03-261-2/+5
| | | | | | | | | | | As pointed out by Richard Sandiford, my recent updates to the register scavenger broke targets that use custom spilling (because the new code assumed that if there were no valid spill slots, than spilling would be impossible). I don't have a test case, but it should be possible to create one for Thumb 1, Mips 16, etc. llvm-svn: 178073
* Update PEI's virtual-register-based scavenging to support multiple ↵Hal Finkel2013-03-261-2/+2
| | | | | | | | | | | | | | | | | | | simultaneous mappings The previous algorithm could not deal properly with scavenging multiple virtual registers because it kept only one live virtual -> physical mapping (and iterated through operands in order). Now we don't maintain a current mapping, but rather use replaceRegWith to completely remove the virtual register as soon as the mapping is established. In order to allow the register scavenger to return a physical register killed by an instruction for definition by that same instruction, we now call RS->forward(I) prior to eliminating virtual registers defined in I. This requires a minor update to forward to ignore virtual registers. These new features will be tested in forthcoming commits. llvm-svn: 178058
* Fix comparison of mixed signednessHal Finkel2013-03-231-1/+1
| | | | | | | | | | | 177774 broke the lld-x86_64-darwin11 builder; error: error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long') for (SI = 0; SI < Scavenged.size(); ++SI) ~~ ^ ~~~~~~~~~~~~~~~~ Fix this by making SI also unsigned. llvm-svn: 177780
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-221-13/+28
| | | | | | | | | | | | | | | | | | This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. llvm-svn: 177774
* Remove ScavengedRC from RegisterScavengingHal Finkel2013-03-221-3/+0
| | | | | | | ScavengedRC was a dead private variable (set, but not otherwise used). No functionality change intended. llvm-svn: 177708
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-311-2/+16
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Remove unneeded #includes.Jakub Staszak2012-11-261-4/+0
| | | | llvm-svn: 168608
* [reg scavenger] Fix the isUsed/isAliasUsed functions so as to not report a falseChad Rosier2012-11-151-1/+1
| | | | | | | | | | | | | | | | positive. In this particular case, R6 was being spilled by the register scavenger when it was in fact dead. The isUsed function reported R6 as used because the R6_R7 alias was reserved (due to the fact that we've reserved R7 as the FP). The solution is to only check if the original register (i.e., R6) isReserved and not the aliases. The aliases are only checked to make sure they're available. The test case is derived from one of the nightly tester benchmarks and is rather intractable and difficult to reproduce, so I haven't included it. rdar://12592448 llvm-svn: 168054
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-151-5/+2
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. llvm-svn: 165983
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-8/+6
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Simplify some more getAliasSet callers.Jakob Stoklund Olesen2012-06-011-7/+4
| | | | | | MCRegAliasIterator can include Reg itself in the list. llvm-svn: 157848
* Add an MRI::tracksLiveness() flag.Jakob Stoklund Olesen2012-03-271-0/+5
| | | | | | | | | | | | | | | | | | | | Late optimization passes like branch folding and tail duplication can transform the machine code in a way that makes it expensive to keep the register liveness information up to date. There is a fuzzy line between register allocation and late scheduling where the liveness information degrades. The MRI::tracksLiveness() flag makes the line clear: While true, liveness information is accurate, and can be used for register scavenging. Once the flag is false, liveness information is not accurate, and can only be used as a hint. Late passes generally don't need the liveness information, but they will sometimes use the register scavenger to help update it. The scavenger enforces strict correctness, and we have to spend a lot of code to update register liveness that may never be used. llvm-svn: 153511
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-3/+3
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-2/+2
| | | | llvm-svn: 152001
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. llvm-svn: 151996
* Track reserved registers separately from RegsAvailable.Jakob Stoklund Olesen2012-02-231-5/+4
| | | | | | | The bulk masking operations from register mask operands don't account for reserved registers. llvm-svn: 151222
* Handle regmasks in RegisterScavenging.Jakob Stoklund Olesen2012-02-221-0/+4
| | | | llvm-svn: 151210
* Fix some scavenger performance issues.Jakob Stoklund Olesen2012-01-291-20/+8
| | | | | | | | | | | | | - Don't call malloc+free in the very hot forward(). - Don't call isTiedToDefOperand(). - Don't create BitVector temporaries. - Merge DeadRegs into KillRegs. - Eliminate the early clobber checks, they were irrelevant to scavenging. - Remove unnecessary code from -Asserts builds. This speeds up ARM PEI by 3.4x and overall llc -O0 codegen time by 11%. llvm-svn: 149189
* Avoid creating BitVector temporaries.Jakob Stoklund Olesen2012-01-291-7/+7
| | | | llvm-svn: 149188
* Give better scavenger errors by invoking the verifier.Jakob Stoklund Olesen2012-01-161-1/+6
| | | | llvm-svn: 148251
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-121-0/+1
| | | | | | when building with assertions disabled. llvm-svn: 137460
* Revert "Don't check liveness of unallocatable registers."Jakob Stoklund Olesen2011-07-301-2/+2
| | | | | | | The ARM target depends on CPSR liveness being tracked after register allocation. llvm-svn: 136548
* Don't check liveness of unallocatable registers.Jakob Stoklund Olesen2011-07-291-2/+2
| | | | | | | | | | | | This includes registers like EFLAGS and ST0-ST7. We don't check for liveness issues in the verifier and scavenger because registers will never be allocated from these classes. While in SSA form, we do care about the liveness of unallocatable unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for MachineDCE and MachineSinking. llvm-svn: 136541
* Handle <def,undef> in the second loop as well.Jakob Stoklund Olesen2011-05-021-1/+3
| | | | llvm-svn: 130718
* Only ignore <undef> use operands, keep the <def,undef> ops.Jakob Stoklund Olesen2011-05-021-1/+4
| | | | | | | | Def operands may also have an <undef> flag, but that just means that a sub-register redef doesn't actually read the super-register. For physical registers, it has no meaning. llvm-svn: 130714
* Add an assertion instead of crashing when the scavenger goes past the endBob Wilson2011-04-051-1/+2
| | | | | | of a basic block. llvm-svn: 128925
* Teach the register scavenger to take subregs into account when finding a ↵Jim Grosbach2011-03-051-5/+10
| | | | | | free register. llvm-svn: 127049
* The scavenger should just use getAllocatableSet() rather than reinventing itJim Grosbach2010-09-021-13/+3
| | | | | | locally. llvm-svn: 112845
* Add a bit of debug output for register scavengingJim Grosbach2010-09-021-2/+12
| | | | llvm-svn: 112787
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-261-2/+2
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* Clean up scavengeRegister() a bit to prefer available regs, which allowsJim Grosbach2010-07-081-3/+6
| | | | | | | | the simplification of frame index register scavenging to not have to check for available registers directly and instead just let scavengeRegister() handle it. llvm-svn: 107880
* When processing frame index virtual registers, consider all available registersJim Grosbach2010-07-081-1/+11
| | | | | | | | (if there are any) and use the one which remains available for the longest rather than just using the first one. This should help enable better re-use of the loaded frame index values. rdar://7318760 llvm-svn: 107847
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-161-2/+6
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. llvm-svn: 106091
* Skip dbg_value instructions when scanning instructions in register scavenging.Jim Grosbach2010-06-041-0/+4
| | | | llvm-svn: 105481
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+2
| | | | llvm-svn: 103193
* Fix PR6847. RegScavenger should ignore DebugValues.Jakob Stoklund Olesen2010-04-151-0/+3
| | | | llvm-svn: 101392
* Eliminate MachineBasicBlock::const_livein_iterator and makeDan Gohman2010-04-131-1/+1
| | | | | | | | MachineBasicBlock::livein_iterator a const_iterator, because clients shouldn't ever be using the iterator interface to mutate the livein set. llvm-svn: 101147
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* RegScavenger::enterBasicBlock should always reset register state.Evan Cheng2009-11-121-5/+2
| | | | llvm-svn: 86972
* - Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests andEvan Cheng2009-10-261-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg around. - Relax register scavenging to allow use of partially "not-live" registers. It's common for targets to operate on registers where the top bits are undef. e.g. s0 = d0 = insert_subreg d0<undef>, s0, 1 ... = d0 When the insert_subreg is eliminated by the coalescer, the scavenger used to complain. The previous fix was to keep to insert_subreg around. But that's brittle and it's overly conservative when we want to use the scavenger to allocate registers. It's actually legal and desirable for other instructions to use the "undef" part of d0. e.g. s0 = d0 = insert_subreg d0<undef>, s0, 1 ... s1 = = s1 = d0 We probably need add a "partial-undef" marker on machine operand so the machine verifier would not complain. llvm-svn: 85091
* When the scavenger is looking for a good candidate location to restore from aJim Grosbach2009-10-251-5/+27
| | | | | | spill, it should avoid doing so inside the live range of a virtual register. llvm-svn: 85026
* The spill restore needs to be resolved to the SP/FP just like the spillJim Grosbach2009-10-211-0/+2
| | | | llvm-svn: 84792
* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-191-3/+2
| | | | | | | | | | appropriate restore location for the spill as well as perform the actual save and restore. The Thumb1 target uses this to make sure R12 is not clobbered while a spilled scavenger register is live there. llvm-svn: 84554
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. llvm-svn: 83467
* grammarJim Grosbach2009-10-061-1/+1
| | | | llvm-svn: 83378
* In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach2009-10-051-9/+15
| | | | | | | | spill slot. When frame references are via the frame pointer, they will be negative, but Thumb1 load/store instructions only allow positive immediate offsets. Instead, Thumb1 will spill to R12. llvm-svn: 83336
* replace TRI->isVirtualRegister() with TargetRegisterInfo::isVirtualRegister()Jim Grosbach2009-09-301-2/+3
| | | | | | per customary usage llvm-svn: 83137
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