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path: root/llvm/lib/CodeGen/RegisterClassInfo.cpp
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* Have getRegPressureSetLimit take a MachineFunction so that aEric Christopher2015-03-111-2/+2
| | | | | | we can inspect the subtarget and function when computing values. llvm-svn: 231951
* Have TargetRegisterInfo::getLargestLegalSuperClass take aEric Christopher2015-03-101-1/+2
| | | | | | | MachineFunction argument so that it can look up the subtarget rather than using a cached one in some Targets. llvm-svn: 231888
* Silence more static analyzer warnings.Michael Ilseman2014-12-151-0/+2
| | | | | | | | Add in definedness checks for shift operators, null checks when pointers are assumed by the code to be non-null, and explicit unreachables. llvm-svn: 224255
* Move register class name strings to a single array in MCRegisterInfo to ↵Craig Topper2014-11-171-1/+1
| | | | | | | | reduce static table size and number of relocation entries. Indices into the table are stored in each MCRegisterClass instead of a pointer. A new method, getRegClassName, is added to MCRegisterInfo and TargetRegisterInfo to lookup the string in the table. llvm-svn: 222118
* Remove unnecessary TargetMachine.h includes.Eric Christopher2014-10-141-1/+0
| | | | llvm-svn: 219672
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-2/+2
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+2
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | | | | | | define below all header includes in the lib/CodeGen/... tree. While the current modules implementation doesn't check for this kind of ODR violation yet, it is likely to grow support for it in the future. It also removes one layer of macro pollution across all the included headers. Other sub-trees will follow. llvm-svn: 206837
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-3/+3
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* Make comment more explicit.Jim Grosbach2013-12-171-3/+3
| | | | | | | Re-reading the comment I updated in previous commit, it's better to make it more explicit and avoid ambiguity more effectively. llvm-svn: 197458
* Typo. s/reserved/preserved/Jim Grosbach2013-12-171-1/+1
| | | | llvm-svn: 197457
* MI-Sched: Adjust regpressure limits for reserved regs.Andrew Trick2013-06-211-0/+32
| | | | llvm-svn: 184564
* Precompute some information about register costs.Jakob Stoklund Olesen2013-01-121-2/+22
| | | | | | | | | | | Remember the minimum cost of the registers in an allocation order and the number of registers at the end of the allocation order that have the same cost per use. This information can be used to limit the search space for RAGreedy::tryEvict() when looking for a cheaper register. llvm-svn: 172280
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-1/+1
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Use MCPhysReg for RegisterClassInfo allocation orders.Jakob Stoklund Olesen2012-11-291-4/+4
| | | | | | This saves a bit of memory. llvm-svn: 168852
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-151-4/+6
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. llvm-svn: 165983
* Move RegisterClassInfo.h.Andrew Trick2012-06-061-1/+1
| | | | | | Allow targets to access this API. It's required for RegisterPressure. llvm-svn: 158102
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-3/+2
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
| | | | llvm-svn: 152001
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-041-1/+1
| | | | | | static data size. llvm-svn: 151998
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. llvm-svn: 151996
* Add missing staticJakob Stoklund Olesen2012-02-241-3/+3
| | | | llvm-svn: 151396
* Add a -stress-regalloc=<N> option.Jakob Stoklund Olesen2012-02-241-1/+9
| | | | | | | This will limit all register classes to N registers in order to stress test register allocation. llvm-svn: 151379
* Detect proper register sub-classes.Jakob Stoklund Olesen2011-08-051-1/+6
| | | | | | | | | | | | | | | | | Some instructions require restricted register classes, but most of the time that doesn't affect register allocation. For example, some instructions don't work with the stack pointer, but that is a reserved register anyway. Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For such a proper sub-class, the register allocator should try to enable register class inflation since that makes more registers available for allocation. Make sure only legal super-classes are considered. For example, tGPR is not a proper sub-class in Thumb mode, but in ARM mode it is. llvm-svn: 136981
* Add TargetRegisterInfo::getRawAllocationOrder().Jakob Stoklund Olesen2011-06-161-5/+3
| | | | | | | | | | | | | This virtual function will replace allocation_order_begin/end as the one to override when implementing custom allocation orders. It is simpler to have one function return an ArrayRef than having two virtual functions computing different ends of the same array. Use getRawAllocationOrder() in place of allocation_order_begin() where it makes sense, but leave some clients that look like they really want the filtered allocation orders from RegisterClassInfo. llvm-svn: 133170
* Include callee-saved registers in debug output.Jakob Stoklund Olesen2011-06-131-1/+1
| | | | llvm-svn: 132899
* Don't try to be clever, just preserve the target's allocation order.Jakob Stoklund Olesen2011-06-061-11/+6
| | | | | | | | | | | | | | | The order of registers returned by getCalleeSavedRegs is used to lay out the fixed stack slots for CSRs. Some targets like their CSRs used from one end, and some targets want them used from the other end. When computing an allocation order, simply preserve the relative ordering of CSRs that the target specifies in its allocation order. Reordering CSRs would break some targets, ARM in particular. We still place volatiles before the CSRs, providing slightly better results with different calling conventions. llvm-svn: 132680
* Preserve the original ordering when a CSR has multiple aliases.Jakob Stoklund Olesen2011-06-031-2/+14
| | | | | | | | Previously, these aliases would be ordered alphabetically. (BH, BL) Print out the computed allocation orders. llvm-svn: 132580
* Just use a SmallVector.Jakob Stoklund Olesen2011-06-021-1/+2
| | | | | | | | | I was confused whether new uint8_t[] would zero-initialize the returned array, and it seems that so is gcc-4.0. This should fix the test failures on darwin 9. llvm-svn: 132500
* Start with a zeroed CSRNum map.Benjamin Kramer2011-06-021-1/+1
| | | | | | Found by valgrind. llvm-svn: 132457
* Initialize members to fix problem found by valgrind.Jakob Stoklund Olesen2011-06-021-2/+3
| | | | llvm-svn: 132456
* Add a RegisterClassInfo class that lazily caches information aboutJakob Stoklund Olesen2011-06-021-0/+105
register classes. It provides information for each register class that cannot be determined statically, like: - The number of allocatable registers in a class after filtering out the reserved and invalid registers. - The preferred allocation order with registers that overlap callee-saved registers last. - The last callee-saved register that overlaps a given physical register. This information usually doesn't change between functions, so it is reused for compiling multiple functions when possible. The many possible combinations of reserved and callee saves registers makes it unfeasible to compute this information statically in TableGen. Use RegisterClassInfo to count available registers in various heuristics in SimpleRegisterCoalescing, making the pass run 4% faster. llvm-svn: 132450
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