| Commit message (Collapse) | Author | Age | Files | Lines |
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PBQP allocator. Problem construction is now done exclusively with the new builders.
llvm-svn: 115502
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whether LiveIntervals::getInstructionFromIndex(def) returns NULL.
llvm-svn: 114791
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to hide the gory details.
Allocator instances can now be created by calling createPBQPRegisterAllocator.
Tidied up use of CoalescerPair as per Jakob's suggestions.
Made the new PBQPBuilder based construction process the default. The internal construction process
remains in-place and available via -pbqp-builder=false for now. It will be removed shortly if the new
process doesn't cause any regressions.
llvm-svn: 114626
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llvm-svn: 114431
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between pairs of virtuals, and between virtuals and physicals).
llvm-svn: 114429
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llvm-svn: 114284
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llvm-svn: 114273
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class can be extended to support custom constraints.
For now the allocator still uses the old (internal) construction mechanism by default. This will be phased out soon assuming
no issues with the builder system come up.
To invoke the new construction mechanism just pass '-regalloc=pbqp -pbqp-builder' to llc. To provide custom constraints a
Target just needs to extend PBQPBuilder and pass an instance of their derived builder to the RegAllocPBQP constructor.
llvm-svn: 114272
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intervals, and where the uses and defs of the original intervals were in the original code.
Spill intervals can be hidden using the "-rmf-intervals=virt-nospills*" option.
llvm-svn: 112811
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PBQP version.
llvm-svn: 112742
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llvm-svn: 110460
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llvm-svn: 110410
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address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
llvm-svn: 110396
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Updated renderer to use allocation information from VirtRegMap (if
available) to render spilled intervals differently.
llvm-svn: 108815
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pressure estimates and liveness alongside.
Still experimental.
llvm-svn: 108698
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require
LoopSplitter be run prior to register allocation.
Entirely for testing purposes at the moment.
llvm-svn: 108634
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any command line paramater changed the register allocation produced by
PBQP.
Turns out variety is not the spice of life.
Fixed some comparators, added others. All good now.
llvm-svn: 108613
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TII::isMoveInstr is going tobe completely removed.
llvm-svn: 108507
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physical register can be allocated in the class of the virtual are sufficient.
I think that the test for virtual registers is more strict than it needs to be,
it should be possible to coalesce two virtual registers the class of one
is a subclass of the other.
llvm-svn: 108118
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patch by Evzen Muller!
llvm-svn: 103876
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out by Russell Wallace.
llvm-svn: 96579
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live-in sets or run the rewriter.
llvm-svn: 96450
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Previously spill registers, whose def indexes are not defined, would sometimes be improperly marked as coalescable with conflicting registers. The new findCoalesces routine conservatively assumes that any register with at least one undefined def is not coalescable with any register it interferes with.
llvm-svn: 95636
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* Fixed a reduction bug which occasionally led to infinite-cost (invalid)
register allocation solutions despite the existence finite-cost solutions.
* Significantly reduced memory usage (>50% reduction).
* Simplified a lot of the solver code.
llvm-svn: 94514
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llvm-svn: 92586
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own pass: CalculateSpillWeights.
llvm-svn: 91273
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might otherwise lead to miscompilations.
llvm-svn: 88829
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This introduces a new pass, SlotIndexes, which is responsible for numbering
instructions for register allocation (and other clients). SlotIndexes numbering
is designed to match the existing scheme, so this patch should not cause any
changes in the generated code.
For consistency, and to avoid naming confusion, LiveIndex has been renamed
SlotIndex.
The processImplicitDefs method of the LiveIntervals analysis has been moved
into its own pass so that it can be run prior to SlotIndexes. This was
necessary to match the existing numbering scheme.
llvm-svn: 85979
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Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
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llvm-svn: 83254
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llvm-svn: 82355
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about by icc (#593, partial). Patch by Erick Tryzelaar.
llvm-svn: 81115
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a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.
llvm-svn: 81040
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avoid reloads by reusing clobbered registers.
This was causing issues in 256.bzip2 when compiled with PIC for
a while (starting at r78217), though the problem has since been masked.
llvm-svn: 80872
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llvm-svn: 79564
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llvm-svn: 79397
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llvm-svn: 79378
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llvm-svn: 78840
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llvm-svn: 78667
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llvm-svn: 78664
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register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg.
llvm-svn: 78620
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llvm-svn: 78601
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llvm-svn: 78447
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based solver, but I'll be working to improve that. The PBQP allocator has been updated to use the new solver.
llvm-svn: 78354
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llvm-svn: 77754
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- Some clients which used DOUT have moved to DEBUG. We are deprecating the
"magic" DOUT behavior which avoided calling printing functions when the
statement was disabled. In addition to being unnecessary magic, it had the
downside of leaving code in -Asserts builds, and of hiding potentially
unnecessary computations.
llvm-svn: 77019
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llvm-svn: 73634
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MachineRegisterInfo. This allows more passes to set them.
llvm-svn: 73346
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llvm-svn: 72604
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for PostRAScheduler.
llvm-svn: 71991
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