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path: root/llvm/lib/CodeGen/RegAllocLinearScan.cpp
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* Removed VNInfo::isDefAccurate(). Def "accuracy" can be checked by testing ↵Lang Hames2010-09-251-5/+3
| | | | | | whether LiveIntervals::getInstructionFromIndex(def) returns NULL. llvm-svn: 114791
* Tweak to ignoring reserved regs. The allocator was occasionally still lookingJim Grosbach2010-09-011-2/+4
| | | | | | | at them since they'd end up in the register weights list. Tell it to stop doing that. llvm-svn: 112756
* tidy up trailing whitespace and an 80 column violation.Jim Grosbach2010-09-011-24/+25
| | | | llvm-svn: 112746
* cleanup per feedback. use a helper function for getting the first non-reservedJim Grosbach2010-09-011-17/+14
| | | | | | | physical register in a register class. Make sure to assert if the register class is empty. llvm-svn: 112743
* The register allocator shouldn't consider allocating reserved registers.Jim Grosbach2010-09-011-5/+30
| | | | | | r112728 did this for fast regalloc. llvm-svn: 112741
* Clean up the Spiller.h interface.Jakob Stoklund Olesen2010-08-131-6/+11
| | | | | | | | | The earliestStart argument is entirely specific to linear scan allocation, and can be easily calculated by RegAllocLinearScan. Replace std::vector with SmallVector. llvm-svn: 111055
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* GrammarJim Grosbach2010-07-271-3/+3
| | | | llvm-svn: 109525
* Fix batch of converting RegisterPass<> to INTIALIZE_PASS().Owen Anderson2010-07-211-2/+2
| | | | llvm-svn: 109045
* Change the createSpiller interface to take a MachineFunctionPass argument.Jakob Stoklund Olesen2010-07-201-1/+1
| | | | | | | | The spillers can pluck the analyses they need from the pass reference. Switch some never-null pointers to references. llvm-svn: 108969
* Spillers may alter MachineLoopInfo when breaking critical edges, so make itJakob Stoklund Olesen2010-07-191-2/+2
| | | | | | non-const. llvm-svn: 108734
* Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.Jakob Stoklund Olesen2010-07-161-31/+9
| | | | | | TII::isMoveInstr is going tobe completely removed. llvm-svn: 108507
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-081-2/+21
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
* 80-col fixup.Eric Christopher2010-07-021-1/+2
| | | | llvm-svn: 107537
* Don't return a std::vector in the Spiller interface, but take a reference to aJakob Stoklund Olesen2010-06-241-5/+2
| | | | | | | | vector instead. This avoids needless copying and allocation. Add documentation. llvm-svn: 106788
* improve portability to systems that don't have powf/modf (e.g. solaris 9)Chris Lattner2010-05-151-1/+1
| | | | | | patch by Evzen Muller! llvm-svn: 103876
* rename llvm::llvm_report_error -> llvm::report_fatal_errorChris Lattner2010-04-071-1/+1
| | | | llvm-svn: 100709
* Remove dead codeJakob Stoklund Olesen2010-02-261-4/+0
| | | | llvm-svn: 97261
* Change errs() to dbgs().David Greene2010-01-051-32/+32
| | | | llvm-svn: 92583
* Fix a bunch of little errors that Clang complains about when its being pedanticDouglas Gregor2009-12-191-1/+1
| | | | llvm-svn: 91764
* Moved spill weight calculation out of SimpleRegisterCoalescing and into its ↵Lang Hames2009-12-141-0/+2
| | | | | | own pass: CalculateSpillWeights. llvm-svn: 91273
* Also attempt trivial coalescing for live intervals that end in a copy.Jakob Stoklund Olesen2009-12-101-44/+54
| | | | | | | | | | | | | | | The coalescer is supposed to clean these up, but when setting up parameters for a function call, there may be copies to physregs. If the defining instruction has been LICM'ed far away, the coalescer won't touch it. The register allocation hint does not always work - when the register allocator is backtracking, it clears the hints. This patch is more conservative than r90502, and does not break 483.xalancbmk/i686. It still breaks the PowerPC bootstrap, so it is disabled by default, and can be enabled with the -trivial-coalesce-ends option. llvm-svn: 91049
* Added a new "splitting" spiller.Lang Hames2009-12-091-9/+6
| | | | | | | | | | | | | When a call is placed to spill an interval this spiller will first try to break the interval up into its component values. Single value intervals and intervals which have already been split (or are the result of previous splits) are spilled by the default spiller. Splitting intervals as described above may improve the performance of generated code in some circumstances. This work is experimental however, and it still miscompiles many benchmarks. It's not recommended for general use yet. llvm-svn: 90951
* Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail.Bill Wendling2009-12-051-48/+44
| | | | llvm-svn: 90653
* Also attempt trivial coalescing for live intervals that end in a copy.Jakob Stoklund Olesen2009-12-041-44/+48
| | | | | | | | | | | | | The coalescer is supposed to clean these up, but when setting up parameters for a function call, there may be copies to physregs. If the defining instruction has been LICM'ed far away, the coalescer won't touch it. The register allocation hint does not always work - when the register allocator is backtracking, it clears the hints. This patch takes care of a few more cases that r90163 missed. llvm-svn: 90502
* Cleanups.David Greene2009-11-201-3/+6
| | | | | | Make things a little more efficient as suggested by Evan. llvm-svn: 89489
* Removed references to LiveStacks from Spiller.* . They're no longer needed.Lang Hames2009-11-201-1/+1
| | | | llvm-svn: 89422
* Fix a small bug.David Greene2009-11-191-1/+1
| | | | | | | Fix one case we missed to make sure we reserve registers from allocation. llvm-svn: 89376
* Add support for spreading register allocation.David Greene2009-11-191-7/+60
| | | | | | | | | | | | | Add a -linearscan-skip-count argument (default to 0) that tells the allocator to remember the last N registers it allocated and skip them when looking for a register candidate. This tends to spread out register usage and free up post-allocation scheduling at the cost of slightly more register pressure. The primary benefit is the ability to backschedule reloads. This is turned off by default. llvm-svn: 89356
* Added a new Spiller implementation which wraps ↵Lang Hames2009-11-191-18/+3
| | | | | | | | | | LiveIntervals::addIntervalsForSpills. All spiller calls in RegAllocLinearScan now go through the new Spiller interface. The "-new-spill-framework" command line option has been removed. To use the trivial in-place spiller you should now pass "-spiller=trivial -rewriter=trivial". (Note the trivial spiller/rewriter are only meant to serve as examples of the new in-place modification work. Enabling them will yield terrible, though hopefully functional, code). llvm-svn: 89311
* The Indexes Patch.Lang Hames2009-11-031-23/+32
| | | | | | | | | | | | | | | | This introduces a new pass, SlotIndexes, which is responsible for numbering instructions for register allocation (and other clients). SlotIndexes numbering is designed to match the existing scheme, so this patch should not cause any changes in the generated code. For consistency, and to avoid naming confusion, LiveIndex has been renamed SlotIndex. The processImplicitDefs method of the LiveIntervals analysis has been moved into its own pass so that it can be run prior to SlotIndexes. This was necessary to match the existing numbering scheme. llvm-svn: 85979
* Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky2009-10-251-1/+0
| | | | | | VISIBILITY_HIDDEN removal. llvm-svn: 85043
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-1/+1
| | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. llvm-svn: 85042
* Renamed MachineInstrIndex to LiveIndex.Lang Hames2009-10-031-12/+12
| | | | llvm-svn: 83254
* Simplify a few more uses of reg_iterator.Dan Gohman2009-09-251-3/+3
| | | | llvm-svn: 82812
* Replaces uses of unsigned for indexes in LiveInterval and VNInfo withLang Hames2009-09-041-22/+25
| | | | | | | | a new class, MachineInstrIndex, which hides arithmetic details from most clients. This is a step towards allowing the register allocator to update/insert code during allocation. llvm-svn: 81040
* Kill off more cerr/cout uses and prune includes a bit.Benjamin Kramer2009-08-231-1/+1
| | | | llvm-svn: 79852
* Convert DOUT to DEBUG(errs()...).Bill Wendling2009-08-221-55/+67
| | | | llvm-svn: 79756
* Use setPreservesAll and setPreservesCFG in CodeGen passes.Dan Gohman2009-07-311-0/+1
| | | | llvm-svn: 77754
* More migration to raw_ostream, the water has dried up around the iostream hole.Daniel Dunbar2009-07-251-1/+3
| | | | | | | | | | - Some clients which used DOUT have moved to DEBUG. We are deprecating the "magic" DOUT behavior which avoided calling printing functions when the statement was disabled. In addition to being unnecessary magic, it had the downside of leaving code in -Asserts builds, and of hiding potentially unnecessary computations. llvm-svn: 77019
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* Removed some junk code that snuck in to an earlier commit.Lang Hames2009-07-131-5/+0
| | | | llvm-svn: 75450
* Convert more assert(0)+abort() -> LLVM_UNREACHABLE,Torok Edwin2009-07-111-3/+4
| | | | | | and abort()/exit() -> llvm_report_error(). llvm-svn: 75363
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves ↵Evan Cheng2009-07-011-31/+0
| | | | | | the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. llvm-svn: 74580
* Add a bit IsUndef to MachineOperand. This indicates the def / use register ↵Evan Cheng2009-06-301-0/+11
| | | | | | | | | | operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. llvm-svn: 74518
* - Update register allocation hint after coalescing. This is done by the ↵Evan Cheng2009-06-181-2/+8
| | | | | | | | | target since the hint is target dependent. This is important for ARM register pair hints. - Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping. - More fixes to get ARM load / store double word working. llvm-svn: 73671
* VNInfo cleanup.Lang Hames2009-06-171-3/+3
| | | | llvm-svn: 73634
* Part 1.Evan Cheng2009-06-151-12/+13
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
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