| Commit message (Collapse) | Author | Age | Files | Lines |
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which denotes the register we would like to be assigned to (virtual or
physical). In register allocation, if this hint exists and we can map
it to a physical register (it is either a physical register or it is a
virtual register that already got assigned to a physical one) we use
that register if it is available instead of a random one in the free
pool.
llvm-svn: 10634
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llvm-svn: 10604
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allocation in the presence of preallocated intervals.
llvm-svn: 10595
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llvm-svn: 10570
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nesting level when computing it. Right now the allocator uses:
w = sum_over_defs_uses( 10 ^ nesting level );
llvm-svn: 10569
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for live ranges that fall into assigned registers' holes.
llvm-svn: 10566
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Add a statistic for # reloads
llvm-svn: 10518
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instruction pass. This also fixes all remaining bugs for this new
allocator to pass all tests under test/Programs.
llvm-svn: 10515
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are not reserved registers.
llvm-svn: 10514
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llvm-svn: 10511
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a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
llvm-svn: 10461
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register too.
llvm-svn: 10450
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llvm-svn: 10448
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llvm-svn: 10447
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potential register assignment.
llvm-svn: 10291
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llvm-svn: 10288
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bug where spill instructions were added to the next basic block
instead of the end of the current one if the instruction that required
the spill was the last in the block.
llvm-svn: 10272
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llvm-svn: 10268
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most tests under test/Programs/SingleSource/Benchmarks/Shootout so development will continue on trunk. The allocator is not enabled by default. You will need to pass -regallo=linearscan to lli or llc to use it.
llvm-svn: 10103
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