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path: root/llvm/lib/CodeGen/RegAllocFast.cpp
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* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-101-6/+3
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* Obvious unnecessary loop removal. Follow through from previous checkin.Andrew Trick2012-01-311-11/+10
| | | | llvm-svn: 149398
* RAFast: Generalize the logic for return operands.Andrew Trick2012-01-311-20/+59
| | | | | | | | This removes implicit assumption about the form of MI coming into regalloc. In particular, it should be independent of ProcessImplicitDefs which will eventually become a standard part of coming out of SSA--unless we simply can eliminate IMPLICIT_DEF completely. Current unit tests expose this once I remove incidental pass ordering restrictions. This is not a final fix. Just a temporary workaround until I figure out the right way. llvm-svn: 149360
* Freeze reserved registers before starting register allocation.Jakob Stoklund Olesen2012-01-051-0/+1
| | | | | | | | | | | The register allocators don't currently support adding reserved registers while they are running. Extend the MRI API to keep track of the set of reserved registers when register allocation started. Target hooks like hasFP() and needsStackRealignment() can look at this set to avoid reserving more registers during register allocation. llvm-svn: 147577
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-3/+3
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* If a register is both an early clobber and part of a tied use, handle the useRafael Espindola2011-11-221-7/+16
| | | | | | | | before the clobber so that we copy the value if needed. Fixes pr11415. llvm-svn: 145056
* Insert modified DBG_VALUE into LiveDbgValueMap. Devang Patel2011-11-151-1/+1
| | | | llvm-svn: 144696
* Better diagnostics when inline asm fails to allocate.Jakob Stoklund Olesen2011-07-021-10/+4
| | | | | | | | asm.c:2:7: error: ran out of registers during register allocation asm(""::"r"(0), "r"(1), "r"(2), "r"(3), "r"(4), "r"(5), "r"(6), "r"(7), "r"(8), "r"(9)); ^ llvm-svn: 134310
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-7/+7
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Print registers by name instead of by number.Jakob Stoklund Olesen2011-06-281-6/+7
| | | | llvm-svn: 134013
* After register is spilled there should not be any DBG_VALUE referring the ↵Devang Patel2011-06-211-1/+3
| | | | | | same register. llvm-svn: 133569
* There could be more than one DBG_VALUE instructions for variables where all ↵Devang Patel2011-06-211-4/+6
| | | | | | of them have offset based on one register. llvm-svn: 133560
* Be less aggressive about hinting in RAFast.Jakob Stoklund Olesen2011-06-131-7/+5
| | | | | | | | | | In particular, don't spill dirty registers only to satisfy a hint. It is not worth it. The attached test case provides an example where the fast allocator would spill a register when other registers are available. llvm-svn: 132900
* Avoid calling TRI->getAllocatableSet in RAFast.Jakob Stoklund Olesen2011-06-021-9/+4
| | | | | | | | | | | | | | When compiling a program with lots of small functions like 483.xalancbmk, this makes RAFast 11% faster. Add some comments to clarify the difference between unallocatable and reserved registers. It's quite subtle. The fast register allocator depends on EFLAGS' not being allocatable on x86. That way it can completely avoid tracking liveness, and it won't mind when there are multiple uses of a single def. llvm-svn: 132514
* Use RegisterClassInfo::getOrder in RAFast.Jakob Stoklund Olesen2011-06-021-10/+7
| | | | | | | This saves two virtual function calls and an Allocatable BitVector test, making RAFast run 2% faster. llvm-svn: 132471
* TypoEvan Cheng2011-04-221-1/+1
| | | | llvm-svn: 129970
* Fix a bug where we were counting the alias sets as completely usedEric Christopher2011-04-181-5/+0
| | | | | | | | | registers for fast allocation a different way. This has us updating used registers only when we're using that exact register. Fixes rdar://9207598 llvm-svn: 129711
* Temporarily revert r129408 to see if it brings the bots back.Eric Christopher2011-04-131-0/+2
| | | | llvm-svn: 129417
* Fix a bug where we were counting the alias sets as completely usedEric Christopher2011-04-121-2/+0
| | | | | | | | registers for fast allocation. Fixes rdar://9207598 llvm-svn: 129408
* Add more comments... err debug statements to the fast allocator.Eric Christopher2011-04-121-3/+16
| | | | llvm-svn: 129400
* Fix typo.Eric Christopher2011-04-121-1/+1
| | | | llvm-svn: 129334
* Mark that the return is using EAX so that we don't use it for some otherNick Lewycky2011-02-041-0/+21
| | | | | | purpose. Fixes PR9080! llvm-svn: 124903
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-4/+5
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Remove MachineRegisterInfo::getLastVirtReg(), it was giving wrong resultsJakob Stoklund Olesen2011-01-091-2/+1
| | | | | | | | | | | | | | | | | | when no virtual registers have been allocated. It was only used to resize IndexedMaps, so provide an IndexedMap::resize() method such that Map.grow(MRI.getLastVirtReg()); can be replaced with the simpler Map.resize(MRI.getNumVirtRegs()); This works correctly when no virtuals are allocated, and it bypasses the to/from index conversions. llvm-svn: 123130
* Replace TargetRegisterInfo::printReg with a PrintReg class that also works ↵Jakob Stoklund Olesen2011-01-091-10/+10
| | | | | | | | | | without a TRI instance. Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. llvm-svn: 123107
* Fix comment.Eric Christopher2010-12-081-1/+1
| | | | llvm-svn: 121285
* Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson2010-10-191-1/+4
| | | | | | | | | | | | | | | | | exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. llvm-svn: 116820
* Add DEBUG message.Devang Patel2010-09-101-2/+6
| | | | llvm-svn: 113614
* previous patch was a little too tricky for its own good. Don't try toJim Grosbach2010-09-031-8/+7
| | | | | | | | overload UserInInstr. Explicitly check Allocatable. The early exit in the condition will mean the performance impact of the extra test should be minimal. llvm-svn: 113016
* The register allocator shouldn't consider allocating reserved registers.Jim Grosbach2010-09-011-3/+7
| | | | llvm-svn: 112728
* tidy up a few 80-column and trailing whitespace bits.Jim Grosbach2010-09-011-16/+19
| | | | llvm-svn: 112726
* Ignore unallocatable registers in RegAllocFast.Jakob Stoklund Olesen2010-08-311-1/+2
| | | | llvm-svn: 112632
* Delete dead comment.Eli Friedman2010-08-211-2/+1
| | | | llvm-svn: 111744
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* While emitting DBG_VALUE for registers spilled at the end of a block do not ↵Devang Patel2010-08-061-1/+8
| | | | | | use location of MBB->end(). If a block does not have terminator then incoming iterator points to end(). llvm-svn: 110411
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* While spilling live registers at the end of block check whether they are ↵Devang Patel2010-08-041-1/+24
| | | | | | used by DBG_VALUE machine instructions or not. If a spilled register is used by DBG_VALUE machine instruction then insert a new DBG_VALUE machine instruction to encode variable's new location on stack. llvm-svn: 110235
* Fix a bug in the -regalloc=fast handling of exotic two-address instruction withJakob Stoklund Olesen2010-07-291-3/+11
| | | | | | | | | | | | | | | | | multiple defs, like t2LDRSB_POST. The first def could accidentally steal the physreg that the second, tied def was required to be allocated to. Now, the tied use-def is treated more like an early clobber, and the physreg is reserved before allocating the other defs. This would never be a problem when the tied def was the only def which is the usual case. This fixes MallocBench/gs for thumb2 -O0. llvm-svn: 109715
* Fix memory leak reported by valgrind. Devang Patel2010-07-191-23/+31
| | | | | | Do not visit operands of old instruction. Visit all operands of new instruction. llvm-svn: 108767
* Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.Jakob Stoklund Olesen2010-07-161-6/+2
| | | | | | TII::isMoveInstr is going tobe completely removed. llvm-svn: 108507
* Update DBG_VALUE to refer appropriate stack slot in case of a spill.Devang Patel2010-07-091-2/+19
| | | | llvm-svn: 108023
* Detect and handle COPY in many places.Jakob Stoklund Olesen2010-07-031-3/+10
| | | | | | | This code is transitional, it will soon be possible to eliminate isExtractSubreg, isInsertSubreg, and isMoveInstr in most places. llvm-svn: 107547
* Fix the handling of partial redefines in the fast register allocator.Jakob Stoklund Olesen2010-06-291-17/+39
| | | | | | | | | | | A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. llvm-svn: 107193
* Add more special treatment for inline asm in RegAllocFast.Jakob Stoklund Olesen2010-06-281-21/+107
| | | | | | | | | | | | When an instruction has tied operands and physreg defines, we must take extra care that the tied operands conflict with neither physreg defs nor uses. The special treatment is given to inline asm and instructions with tied operands / early clobbers and physreg defines. This fixes PR7509. llvm-svn: 107043
* Avoid processing early clobbers twice in RegAllocFast.Jakob Stoklund Olesen2010-06-151-3/+8
| | | | | | | | | Early clobbers defining a virtual register were first alocated to a physreg and then processed as a physreg EC, spilling the virtreg. This fixes PR7382. llvm-svn: 105998
* Keep track of the call instructions whose clobber lists were skipped during fastJakob Stoklund Olesen2010-06-041-0/+17
| | | | | | | | | | | register allocation. Process all of the clobber lists at the end of the function, marking the registers as used in MachineRegisterInfo. This is necessary in case the calls clobber callee-saved registers (sic). llvm-svn: 105473
* Add support for partial redefs to the fast register allocator.Jakob Stoklund Olesen2010-05-191-20/+18
| | | | | | | | | | A partial redef now triggers a reload if required. Also don't add <imp-def,dead> operands for physical superregisters. Kill flags are still treated as full register kills, and <imp-use,kill> operands are added for physical superregisters as before. llvm-svn: 104167
* Properly handle multiple definitions of a virtual register in the sameJakob Stoklund Olesen2010-05-181-21/+41
| | | | | | | | | | | | | | | instruction. This can happen on ARM: >> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0 Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031* Killing last use: %reg1028 Allocating %reg1035 from QPR Assigning %reg1035 to Q1 << %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def> llvm-svn: 104056
* Pull the UsedInInstr.test() calls into calcSpillCost() and remember aliases.Jakob Stoklund Olesen2010-05-171-5/+5
| | | | | | | This fixes the miscompilations of MultiSource/Applications/JM/l{en,de}cod. Clang now successfully self hosts in a debug build with the fast register allocator. llvm-svn: 103975
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