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* Under normal circumstances, when a frame pointer is not required, we reserveEvan Cheng2007-05-011-17/+14
| | | | | | | | | | | | argument space for call sites in the function immediately on entry to the current function. This eliminates the need for add/sub sp brackets around call sites. However, this is not always a good idea. If the "call frame" is large and the target load / store instructions have small immediate field to encode sp offset, this can cause poor codegen. In the worst case, this can make it impossible to scavenge a register if the reserved spill slot is pushed too far apart from sp / fp. llvm-svn: 36607
* Match MachineFunction::UsedPhysRegs changes.Evan Cheng2007-04-251-3/+2
| | | | llvm-svn: 36452
* support for >4G stack framesChris Lattner2007-04-251-1/+1
| | | | llvm-svn: 36425
* support > 4G stack objectsChris Lattner2007-04-251-2/+2
| | | | llvm-svn: 36422
* Fix a bug introduced with my previous patch, where it didn't correctly handleChris Lattner2007-04-091-7/+9
| | | | | | | instructions which replace themselves when FI's are rewritten (common on ppc). This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll llvm-svn: 35789
* Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308:Chris Lattner2007-04-091-1/+5
| | | | | | | some instructions can have multiple frame indices in them. If this happens, rewrite all of them. llvm-svn: 35785
* If target decides to create an emergency spill slot, make sure it's closest ↵Evan Cheng2007-03-061-7/+56
| | | | | | to SP or frame pointer. llvm-svn: 34965
* Delete register scavenger when done with it.Evan Cheng2007-03-011-0/+2
| | | | llvm-svn: 34786
* Interface clean up.Evan Cheng2007-03-011-1/+1
| | | | llvm-svn: 34772
* add a newline at end of fileChris Lattner2007-02-281-0/+1
| | | | llvm-svn: 34735
* Make requiresRegisterScavenging determination on a per MachineFunction basis.Evan Cheng2007-02-281-1/+1
| | | | llvm-svn: 34711
* MRegisterInfo disowns RegScavenger. It's immutable.Evan Cheng2007-02-281-2/+2
| | | | llvm-svn: 34706
* Let MRegisterInfo now owns RegScavenger.Evan Cheng2007-02-271-3/+3
| | | | llvm-svn: 34691
* forward() should not increment internal iterator. Its client may insert ↵Evan Cheng2007-02-271-1/+1
| | | | | | instruction between now and next forward() call. llvm-svn: 34649
* First potential client of register scavenger.Evan Cheng2007-02-231-4/+13
| | | | llvm-svn: 34516
* Change the MachineDebugInfo to MachineModuleInfo to better reflect usageJim Laskey2007-01-261-3/+3
| | | | | | for debugging and exception handling. llvm-svn: 33550
* Added a MRegisterInfo hook that tells PEI the target is responsible forEvan Cheng2007-01-251-2/+3
| | | | | | rounding the stack frame to a multiple of stack alignment. llvm-svn: 33504
* PEI is now responsible for adding MaxCallFrameSize to frame size and align ↵Evan Cheng2007-01-231-1/+16
| | | | | | the stack. Each target can further adjust the frame size if necessary. llvm-svn: 33460
* Remove an unused variable.Evan Cheng2007-01-201-1/+0
| | | | llvm-svn: 33396
* We not align the final stack slot but instead let the target do so in ↵Evan Cheng2007-01-201-7/+0
| | | | | | emitPrologue(). Each target can make adjustments to the stack frame and re-align the stack as it deem appropriate. Do not align it twice which can end up wasting stack space. llvm-svn: 33387
* - Fixing naming inconsistency: calleesave -> calleesaved.Evan Cheng2007-01-021-24/+30
| | | | | | - Make use of spillCalleeSavedRegisters() and restoreCalleeSavedRegisters(). llvm-svn: 32822
* Initialize {Min|Max}CSFrameIndex properly.Evan Cheng2006-12-071-2/+4
| | | | llvm-svn: 32299
* TargetRegisterClass specifies the desired spill alignment. However, it ↵Evan Cheng2006-09-281-1/+6
| | | | | | cannot be honored if stack alignment is smaller. llvm-svn: 30648
* PEI now place callee save spills closest to the address pointed to by theEvan Cheng2006-09-281-11/+67
| | | | | | | incoming stack. This allows X86 backend to use push / pop in epilogue / prologue. llvm-svn: 30636
* Rename function. It's determining which callee-save registers to save.Evan Cheng2006-09-261-7/+7
| | | | llvm-svn: 30616
* s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|Chris Lattner2006-08-271-1/+1
| | | | llvm-svn: 29911
* Tidy up.Jim Laskey2006-08-251-2/+4
| | | | llvm-svn: 29888
* Consolidate callee saved register information so that it can me used by debugJim Laskey2006-08-251-20/+21
| | | | | | information and exception handling. llvm-svn: 29881
* Shave another 27K off libllvmgcc.dylib with visibility hiddenChris Lattner2006-06-281-1/+2
| | | | llvm-svn: 28973
* Remove dead variableChris Lattner2006-05-121-1/+0
| | | | llvm-svn: 28253
* Foundation for call frame information.Jim Laskey2006-04-071-0/+6
| | | | llvm-svn: 27491
* The stack alignment is now computed dynamically, just verify it is correct.Chris Lattner2006-04-031-1/+2
| | | | llvm-svn: 27380
* Always compute max align.Chris Lattner2005-11-061-6/+5
| | | | llvm-svn: 24227
* Add the necessary support to the ISel to allow targets to codegen the newNate Begeman2005-11-061-3/+11
| | | | | | | | alignment information appropriately. Includes code for PowerPC to support fixed-size allocas with alignment larger than the stack. Support for arbitrarily aligned dynamic allocas coming soon. llvm-svn: 24224
* now that we have a reg class to spill with, get this info from the regclassChris Lattner2005-09-301-4/+3
| | | | llvm-svn: 23559
* Now that we have getCalleeSaveRegClasses() info, use it to pass the registerChris Lattner2005-09-301-8/+11
| | | | | | class into the spill/reload methods. Targets can now rely on that argument. llvm-svn: 23556
* Change this code ot pass register classes into the stack slot spiller/reloaderChris Lattner2005-09-301-2/+4
| | | | | | | code. PrologEpilogInserter hasn't been updated yet though, so targets cannot use this info. llvm-svn: 23536
* Fix a bug in my previous patch that was using the wrong iterator. This fixesChris Lattner2005-08-291-1/+1
| | | | | | Olden/bisort among others. llvm-svn: 23124
* Make this code safe for when loadRegFromStackSlot inserts multiple instructions.Chris Lattner2005-08-261-1/+13
| | | | llvm-svn: 23108
* When inserting callee-save register reloads, make sure to skip over anyChris Lattner2005-05-151-0/+8
| | | | | | | terminator instructions before the 'ret' in case the target has a multi-instruction return sequence. llvm-svn: 22041
* Tolerate instrs with extra argsChris Lattner2005-05-131-1/+1
| | | | llvm-svn: 21982
* Remove trailing whitespaceMisha Brukman2005-04-211-12/+12
| | | | llvm-svn: 21420
* Simplify/speedup the PEI by not having to scan for uses of the callee savedChris Lattner2005-01-231-19/+5
| | | | | | | registers. This information is computed directly by the register allocator now. llvm-svn: 19795
* Speed this up a bit by making ModifiedRegs a vector<char> not vector<bool>Chris Lattner2005-01-231-6/+5
| | | | llvm-svn: 19787
* Implicitly defined registers can clobber callee saved registers too!Chris Lattner2005-01-221-0/+6
| | | | | | This fixes the return-address-not-being-saved problem in the Alpha backend. llvm-svn: 19741
* Add an assertion that would have made more sense to duraidChris Lattner2005-01-191-1/+3
| | | | llvm-svn: 19704
* Put this change back in after testing from Reid proved its innocence. ↵Nate Begeman2004-08-291-2/+2
| | | | | | getSpillSize now returns value in bits llvm-svn: 16102
* Back out change to divide getSpillSize by 8 until I figure out why it breaks ↵Nate Begeman2004-08-271-2/+2
| | | | | | x86, which has register sizes in bits. llvm-svn: 16073
* Register sizes are in bits, not bytesNate Begeman2004-08-271-2/+2
| | | | llvm-svn: 16070
* Register info alignment is in bits, frame object alignment is (currently) inChris Lattner2004-08-211-1/+1
| | | | | | bytes. llvm-svn: 15970
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