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* CodeGen: Remove pipeline dependencies on StackProtector; NFCMatthias Braun2018-07-131-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | This re-applies r336929 with a fix to accomodate for the Mips target scheduling multiple SelectionDAG instances into the pass pipeline. PrologEpilogInserter and StackColoring depend on the StackProtector analysis being alive from the point it is run until PEI, which requires that they are all scheduled in the same FunctionPassManager. Inserting a (machine) ModulePass between StackProtector and PEI results in these passes being in separate FunctionPassManagers and the StackProtector is not available for PEI. PEI and StackColoring don't use much information from the StackProtector pass, so transfering the required information to MachineFrameInfo is cleaner than keeping the StackProtector pass around. This commit moves the SSP layout information to MFI instead of keeping it in the pass. This patch set (D37580, D37581, D37582, D37583, D37584, D37585, D37586, D37587) is a first draft of the pagerando implementation described in http://lists.llvm.org/pipermail/llvm-dev/2017-June/113794.html. Patch by Stephen Crane <sjc@immunant.com> Differential Revision: https://reviews.llvm.org/D49256 llvm-svn: 336964
* Revert "(HEAD -> master, origin/master, arcpatch-D37582) CodeGen: Remove ↵Matthias Braun2018-07-121-5/+9
| | | | | | | | | | pipeline dependencies on StackProtector; NFC" This was triggering pass scheduling failures. This reverts commit r336929. llvm-svn: 336934
* CodeGen: Remove pipeline dependencies on StackProtector; NFCMatthias Braun2018-07-121-9/+5
| | | | | | | | | | | | | | | | | | | | | | | PrologEpilogInserter and StackColoring depend on the StackProtector analysis being alive from the point it is run until PEI, which requires that they are all scheduled in the same FunctionPassManager. Inserting a (machine) ModulePass between StackProtector and PEI results in these passes being in separate FunctionPassManagers and the StackProtector is not available for PEI. PEI and StackColoring don't use much information from the StackProtector pass, so transfering the required information to MachineFrameInfo is cleaner than keeping the StackProtector pass around. This commit moves the SSP layout information to MFI instead of keeping it in the pass. This patch set (D37580, D37581, D37582, D37583, D37584, D37585, D37586, D37587) is a first draft of the pagerando implementation described in http://lists.llvm.org/pipermail/llvm-dev/2017-June/113794.html. Patch by Stephen Crane <sjc@immunant.com> Differential Revision: https://reviews.llvm.org/D49256 llvm-svn: 336929
* [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug propertyMikael Holmen2018-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: In some cases, these operands lacked the IsDebug property, which is meant to signal that they should not affect codegen. This patch adds a check for this property in the MachineVerifier and adds it where it was missing. This includes refactorings to use MachineInstrBuilder construction functions instead of manually setting up the intrinsic everywhere. Patch by: JesperAntonsson Reviewers: aprantl, rnk, echristo, javed.absar Reviewed By: aprantl Subscribers: qcolombet, sdardis, nemanjai, JDevlieghere, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D48319 llvm-svn: 335214
* Use MF instead of Fn for MachineFunction references. NFCFrancis Visoiu Mistrih2018-06-051-97/+97
| | | | llvm-svn: 333973
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-11/+13
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [PEI][NFC] Move StackSize opt-remark code next to -warn-stack codeFrancis Visoiu Mistrih2018-02-051-7/+6
| | | | | | | This allows us to make sure we're always having the same sizes in both remarks and warnings. llvm-svn: 324283
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-8/+8
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-3/+3
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-2/+2
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-031-1/+1
| | | | | | | | | | | This header already includes a CodeGen header and is implemented in lib/CodeGen, so move the header there to match. This fixes a link error with modular codegeneration builds - where a header and its implementation are circularly dependent and so need to be in the same library, not split between two like this. llvm-svn: 317379
* [PEI] Simplify handling of targets with no phys regs. NFCFrancis Visoiu Mistrih2017-11-031-13/+3
| | | | | | | | | Make doSpillCalleeSavedRegs a member function, instead of passing most of the members of PEI as arguments. Differential Review: https://reviews.llvm.org/D35642 llvm-svn: 317309
* [NFC] Convert OptimizationRemarkEmitter old emit() calls to new closureVivek Pandya2017-10-111-5/+6
| | | | | | | | | | | | | | parameterized emit() calls Summary: This is not functional change to adopt new emit() API added in r313691. Reviewed By: anemet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38285 llvm-svn: 315476
* [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-10-101-17/+38
| | | | | | other minor fixes (NFC). llvm-svn: 315380
* [PEI] Remove required properties and use 'if' instead of std::functionReid Kleckner2017-10-061-49/+23
| | | | | | | | | | | | | | | | | | Summary: After r303360, we initialize UsesCalleeSaves in runOnMachineFunction, which runs after getRequiredProperties. UsesCalleeSaves was initialized to 'false', so getRequiredProperties would always return an empty set. We don't have a TargetMachine available early anymore after r303360. Just removing the requirement of NoVRegs seems to make things work, so let's do that. Reviewers: thegameg, dschuff, MatzeB Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D38597 llvm-svn: 315089
* [CodeGen] Emit necessary .note sections for -fsplit-stackThan McIntosh2017-09-271-1/+5
| | | | | | | | | | | | | | | | | | | | | Summary: According to https://gcc.gnu.org/wiki/SplitStacks, the linker expects a zero-sized .note.GNU-split-stack section if split-stack is used (and also .note.GNU-no-split-stack section if it also contains non-split-stack functions), so it can handle the cases where a split-stack function calls non-split-stack function. This change adds the sections if needed. Fixes PR #34670. Reviewers: thanm, rnk, luqmana Reviewed By: rnk Subscribers: llvm-commits Patch by Cherry Zhang <cherryyz@google.com> Differential Revision: https://reviews.llvm.org/D38051 llvm-svn: 314335
* Retire the llvm.dbg.mir hack after r311594.Adrian Prantl2017-08-231-3/+0
| | | | llvm-svn: 311610
* Add "Restored" flag to CalleeSavedInfoKrzysztof Parzyszek2017-08-101-2/+2
| | | | | | | | | | | The liveness-tracking code assumes that the registers that were saved in the function's prolog are live outside of the function. Specifically, that registers that were saved are also live-on-exit from the function. This isn't always the case as illustrated by the LR register on ARM. Differential Revision: https://reviews.llvm.org/D36160 llvm-svn: 310619
* Remove PrologEpilogInserter's usage of DBG_VALUE's offset fieldAdrian Prantl2017-08-011-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the last half-dozen commits to LLVM I removed code that became dead after removing the offset parameter from llvm.dbg.value gradually proceeding from IR towards the backend. Before I can move on to DwarfDebug and friends there is one last side-called offset I need to remove: This patch modifies PrologEpilogInserter's use of the DBG_VALUE's offset argument to use a DIExpression instead. Because the PrologEpilogInserter runs at the Machine level I had to play a little trick with a named llvm.dbg.mir node to get the DIExpressions to print in MIR dumps (which print the llvm::Module followed by the MachineFunction dump). I also had to add rudimentary DwarfExpression support to CodeView and as a side-effect also fixed a bug (CodeViewDebug::collectVariableInfo was supposed to give up on variables with complex DIExpressions, but would fail to do so for fragments, which are also modeled as DIExpressions). With this last holdover removed we will have only one canonical way of representing offsets to debug locations which will simplify the code in DwarfDebug (and future versions of CodeViewDebug once it starts handling more complex expressions) and make it easier to reason about. This patch is NFC-ish: All test case changes are for assembler comments and the binary output does not change. rdar://problem/33580047 Differential Revision: https://reviews.llvm.org/D36125 llvm-svn: 309751
* [OptRemark] Allow streaming of 64-bit integersAdam Nemet2017-07-271-1/+1
| | | | llvm-svn: 309293
* [PEI] Fix refactoring from r308664Francis Visoiu Mistrih2017-07-201-1/+1
| | | | llvm-svn: 308666
* [PEI] Separate saving and restoring CSRs into different functions. NFCFrancis Visoiu Mistrih2017-07-201-66/+51
| | | | | | | | | | | Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores. This is mostly useful for future shrink-wrapping improvements where we want to save / restore a specific part of the CSRs in a specific block. Differential Revision: https://reviews.llvm.org/D35644 llvm-svn: 308664
* Revert "[PEI] Simplify handling of targets with no phys regs. NFC"Francis Visoiu Mistrih2017-07-201-8/+23
| | | | | | | | This reverts commit ce30ab6e5598f3c24f59ad016dc9526bc9a1d450. sanitizer-ppc64le-linux seems to segfault when testing the sanitizers. llvm-svn: 308581
* Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"Francis Visoiu Mistrih2017-07-201-51/+66
| | | | | | | | This reverts commit 540f6a26ae932469804a379ce9a8cbe715d59c23. sanitizer-ppc64le-linux seems to segfault when testing the sanitizers. llvm-svn: 308580
* [PEI] Separate saving and restoring CSRs into different functions. NFCFrancis Visoiu Mistrih2017-07-201-66/+51
| | | | | | | | | | | Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores. This is mostly useful for future shrink-wrapping improvements where we want to save / restore a specific part of the CSRs in a specific block. Differential Revision: https://reviews.llvm.org/D35644 llvm-svn: 308573
* Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"Francis Visoiu Mistrih2017-07-201-51/+66
| | | | | | This reverts commit a84d1fa6847e70ebf63594d41a00b473c941bd72. llvm-svn: 308562
* [PEI] Add basic opt-remarks supportFrancis Visoiu Mistrih2017-07-191-0/+13
| | | | | | | | | | Add optimization remarks support to the PrologueEpilogueInserter. For now, emit the stack size as an analysis remark, but more additions wrt shrink-wrapping may be added. https://reviews.llvm.org/D35645 llvm-svn: 308556
* [PEI] Simplify handling of targets with no phys regs. NFCFrancis Visoiu Mistrih2017-07-191-23/+8
| | | | | | | | | Make doSpillCalleeSavedRegs a member function, instead of passing most of the members of PEI as arguments. Differential Revision: https://reviews.llvm.org/D35642 llvm-svn: 308555
* [PEI] Separate saving and restoring CSRs into different functions. NFCFrancis Visoiu Mistrih2017-07-191-66/+51
| | | | | | | | | | | Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores. This is mostly useful for future shrink-wrapping improvements where we want to save / restore a specific part of the CSRs in a specific block. Differential Revision: https://reviews.llvm.org/D35644 llvm-svn: 308554
* Revert "r306529 - [X86] Correct dwarf unwind information in function epilogue"Daniel Jasper2017-06-291-4/+0
| | | | | | | | | | I am 99% sure that this breaks the PPC ASAN build bot: http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/3112/steps/64-bit%20check-asan/logs/stdio If it doesn't go back to green, we can recommit (and fix the original commit message at the same time :) ). llvm-svn: 306676
* [X86] Correct dwarf unwind information in function epiloguePetar Jovanovic2017-06-281-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CFI instructions that set appropriate cfa offset and cfa register are now inserted in emitEpilogue() in X86FrameLowering. Majority of the changes in this patch: 1. Ensure that CFI instructions do not affect code generation. 2. Enable maintaining correct information about cfa offset and cfa register in a function when basic blocks are reordered, merged, split, duplicated. These changes are target independent and described below. Changed CFI instructions so that they: 1. are duplicable 2. are not counted as instructions when tail duplicating or tail merging 3. can be compared as equal Add information to each MachineBasicBlock about cfa offset and cfa register that are valid at its entry and exit (incoming and outgoing CFI info). Add support for updating this information when basic blocks are merged, split, duplicated, created. Add a verification pass (CFIInfoVerifier) that checks that outgoing cfa offset and register of predecessor blocks match incoming values of their successors. Incoming and outgoing CFI information is used by a late pass (CFIInstrInserter) that corrects CFA calculation rule for a basic block if needed. That means that additional CFI instructions get inserted at basic block beginning to correct the rule for calculating CFA. Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D18046 llvm-svn: 306529
* RegisterScavenging: Move scavenging logic from PEI to RegisterScavenging; NFCMatthias Braun2017-06-021-96/+4
| | | | | | | These parts do not depend on any PrologEpilogInserter logic and therefore better fits RegisterScaveging.cpp. llvm-svn: 304596
* AArch64/PEI: Do not add reserved regs to liveinsMatthias Braun2017-05-271-1/+2
| | | | | | | We do not track liveness for reserved registers. It is unnecessary to add them to block livein lists. llvm-svn: 304059
* CodeGen: Rename DEBUG_TYPE to match passnamesMatthias Braun2017-05-251-3/+3
| | | | | | | | Rename the DEBUG_TYPE to match the names of corresponding passes where it makes sense. Also establish the pattern of simply referencing DEBUG_TYPE instead of repeating the passname where possible. llvm-svn: 303921
* [LegacyPassManager] Remove TargetMachine constructorsFrancis Visoiu Mistrih2017-05-181-20/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a new way to access the TargetMachine through TargetPassConfig, as a dependency. The patterns replaced here are: * Passes handling a null TargetMachine call `getAnalysisIfAvailable<TargetPassConfig>`. * Passes not handling a null TargetMachine `addRequired<TargetPassConfig>` and call `getAnalysis<TargetPassConfig>`. * MachineFunctionPasses now use MF.getTarget(). * Remove all the TargetMachine constructors. * Remove INITIALIZE_TM_PASS. This fixes a crash when running `llc -start-before prologepilog`. PEI needs StackProtector, which gets constructed without a TargetMachine by the pass manager. The StackProtector pass doesn't handle the case where there is no TargetMachine, so it segfaults. Related to PR30324. Differential Revision: https://reviews.llvm.org/D33222 llvm-svn: 303360
* ARM: Compute MaxCallFrame size earlyMatthias Braun2017-05-051-0/+3
| | | | | | | | | | | | | | | | | This exposes a method in MachineFrameInfo that calculates MaxCallFrameSize and calls it after instruction selection in the ARM target. This avoids ARMBaseRegisterInfo::canRealignStack()/ARMFrameLowering::hasReservedCallFrame() giving different answers in early/late phases of codegen. The testcase shows a particular nasty example result of that where we would fail to properly align an alloca. Differential Revision: https://reviews.llvm.org/D32622 llvm-svn: 302303
* PEI: Skip dead objects when looking at CSRsMatt Arsenault2017-05-021-0/+3
| | | | | | | | On AMDGPU if an SGPR is spilled to a VGPR, the frame index is deleted. If there were any CSR SGPRs, this woudl assert when setting the offset. llvm-svn: 301961
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-4/+4
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* Use methods to access data stored with frame instructionsSerge Pavlov2017-04-131-11/+4
| | | | | | | | | | | | | Instructions CALLSEQ_START..CALLSEQ_END and their target dependent counterparts keep data like frame size, stack adjustment etc. These data are accessed by getOperand using hard coded indices. It is error prone way. This change implements the access by special methods, which improve readability and allow changing data representation without massive changes of index values. Differential Revision: https://reviews.llvm.org/D31953 llvm-svn: 300196
* Disable Callee Saved RegistersOren Ben Simhon2017-03-141-1/+1
| | | | | | | | | | | | | | Each Calling convention (CC) defines a static list of registers that should be preserved by a callee function. All other registers should be saved by the caller. Some CCs use additional condition: If the register is used for passing/returning arguments – the caller needs to save it - even if it is part of the Callee Saved Registers (CSR) list. The current LLVM implementation doesn’t support it. It will save a register if it is part of the static CSR list and will not care if the register is passed/returned by the callee. The solution is to dynamically allocate the CSR lists (Only for these CCs). The lists will be updated with actual registers that should be saved by the callee. Since we need the allocated lists to live as long as the function exists, the list should reside inside the Machine Register Info (MRI) which is a property of the Machine Function and managed by it (and has the same life span). The lists should be saved in the MRI and populated upon LowerCall and LowerFormalArguments. The patch will also assist to implement future no_caller_saved_regsiters attribute intended for interrupt handler CC. Differential Revision: https://reviews.llvm.org/D28566 llvm-svn: 297715
* [thumb,framelowering] Reset NoVRegs in Thumb1FrameLowering::emitPrologue.Florian Hahn2017-01-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Summary: In this function, virtual registers can be introduced (for example through calls to emitThumbRegPlusImmInReg). doScavengeFrameVirtualRegs will replace those virtual registers with concrete registers later on in PrologEpilogInserter, which sets NoVRegs again. This patch fixes the Codegen/Thumb/segmented-stacks.ll test case which failed with expensive checks. https://llvm.org/bugs/show_bug.cgi?id=27484 Reviewers: rnk, bkramer, olista01 Reviewed By: olista01 Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D28829 llvm-svn: 292372
* TRI: Add hook to pass scavenger during frame eliminationMatt Arsenault2016-11-241-4/+11
| | | | | | | | | | | | The scavenger was not passed if requiresFrameIndexScavenging was enabled. I need to be able to test for the availability of an unallocatable register here, so I can't create a virtual register for it. It might be better to just always use the scavenger and stop creating virtual registers. llvm-svn: 287843
* Modify df_iterator to support post-order actionsDavid Callahan2016-10-051-1/+1
| | | | | | | | | | | | Summary: This makes a change to the state used to maintain visited information for depth first iterator. We know assume a method "completed(...)" which is called after all children of a node have been visited. In all existing cases, this method does nothing so this patch has no functional changes. It will however allow a client to distinguish back from cross edges in a DFS tree. Reviewers: nadav, mehdi_amini, dberlin Subscribers: MatzeB, mzolotukhin, twoh, freik, llvm-commits Differential Revision: https://reviews.llvm.org/D25191 llvm-svn: 283391
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-251-1/+1
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* Revert "RegScavenging: Add scavengeRegisterBackwards()"Matthias Braun2016-08-191-85/+62
| | | | | | | | | | | The ppc64 multistage bot fails on this. This reverts commit r279124. Also Revert "CodeGen: Add/Factor out LiveRegUnits class; NFCI" because it depends on the previous change This reverts commit r279171. llvm-svn: 279199
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2016-08-181-62/+85
| | | | | | | | | | | | | | | | Re-apply r276044 with off-by-1 instruction fix for the reload placement. This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 279124
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-77/+76
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* Revert "RegScavenging: Add scavengeRegisterBackwards()"Matthias Braun2016-07-201-81/+62
| | | | | | | | | Reverting this commit for now as it seems to be causing failures on test-suite tests on the clang-ppc64le-linux-lnt bot. This reverts commit r276044. llvm-svn: 276068
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2016-07-191-62/+81
| | | | | | | | | | | | | | This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 276044
* CodeGen: Use MachineInstr& in PrologEpilogInserter, NFCDuncan P. N. Exon Smith2016-07-011-18/+20
| | | | | | | | | Use MachineInstr& over MachineInstr* to avoid implicit iterator to pointer conversions. MachineInstr*-as-nullptr was being used as a flag for whether the for loop terminated normally; I added an explicit `bool` instead. llvm-svn: 274310
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