| Commit message (Collapse) | Author | Age | Files | Lines |
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This fixes an in-place update bug where code inserted at the end of basic blocks may not be covered by existing intervals which were live across the entire block. It is also consistent with the way ranges are specified for live intervals.
llvm-svn: 91859
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own pass: CalculateSpillWeights.
llvm-svn: 91273
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Patch by Howard Hinnant!
llvm-svn: 90365
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- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
llvm-svn: 88745
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inserted into the numbering.
PreAllocSplitting is now using this API to insert code.
llvm-svn: 88725
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slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
llvm-svn: 87022
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miscompilations casued by PreAllocSplitting.
llvm-svn: 86919
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This patch forbids implicit conversion of DenseMap::const_iterator to
DenseMap::iterator which was possible because DenseMapIterator inherited
(publicly) from DenseMapConstIterator. Conversion the other way around is now
allowed as one may expect.
The template DenseMapConstIterator is removed and the template parameter
IsConst which specifies whether the iterator is constant is added to
DenseMapIterator.
Actually IsConst parameter is not necessary since the constness can be
determined from KeyT but this is not relevant to the fix and can be addressed
later.
Patch by Victor Zverovich!
llvm-svn: 86636
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llvm-svn: 86521
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This introduces a new pass, SlotIndexes, which is responsible for numbering
instructions for register allocation (and other clients). SlotIndexes numbering
is designed to match the existing scheme, so this patch should not cause any
changes in the generated code.
For consistency, and to avoid naming confusion, LiveIndex has been renamed
SlotIndex.
The processImplicitDefs method of the LiveIntervals analysis has been moved
into its own pass so that it can be run prior to SlotIndexes. This was
necessary to match the existing numbering scheme.
llvm-svn: 85979
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Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
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llvm-svn: 84682
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llvm-svn: 84681
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get FixedStack PseudoSourceValues.
llvm-svn: 84326
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llvm-svn: 83608
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llvm-svn: 83589
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llvm-svn: 83255
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llvm-svn: 83254
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require a LiveIntervals instance in future.
llvm-svn: 81374
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a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.
llvm-svn: 81040
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update all code that this affects.
llvm-svn: 79830
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register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg.
llvm-svn: 78620
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llvm-svn: 77754
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rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
llvm-svn: 75900
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llvm-svn: 75423
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and abort()/exit() -> llvm_report_error().
llvm-svn: 75363
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as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.
A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test
condition has been updated to reflect this.
llvm-svn: 75097
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llvm-svn: 73634
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not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.
Not yet enabled. This is part 1. More coming.
llvm-svn: 70787
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register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).
llvm-svn: 68714
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were subtlely wrong in obscure cases. Patch the testcase
to account for this change.
llvm-svn: 68093
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useful with it at the moment, but it will in the future.
llvm-svn: 67012
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llvm-svn: 66158
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This fixes some subtle miscompilations.
llvm-svn: 66147
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Update a testcase to check this.
llvm-svn: 66029
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llvm-svn: 65121
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safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.
llvm-svn: 63936
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between call frame setup/restore points. Unfortunately, this regresses
code size a bit, but at least it's correct now!
llvm-svn: 63837
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direction.
Live interval reconstruction needs to account for this, and scour its maps to
prevent dangling references.
llvm-svn: 63558
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llvm-svn: 63536
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llvm-svn: 63492
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different set iteration order for the reg_iterator.
llvm-svn: 63490
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don't try to insert loads/stores between call frame setup and the actual call.
This fixes the last known failure for the pre-alloc-splitter.
llvm-svn: 63339
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and an iterator invalidation issue.
FreeBench/pifft no longer miscompiles with these fixes!
llvm-svn: 63293
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llvm-svn: 63276
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vast majority of code size regressions introduced by pre-alloc-splitting.
llvm-svn: 63274
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llvm-svn: 63091
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llvm-svn: 63049
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llvm-svn: 63041
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llvm-svn: 63040
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