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* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.Bill Wendling2010-07-151-2/+3
| | | | llvm-svn: 108450
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-24/+4
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* - Do away with SimpleHazardRecognizer.h. It's not used and offers little value.Evan Cheng2010-06-141-25/+0
| | | | | | - Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it. llvm-svn: 105959
* Allow target to provide its own hazard recognizer to post-ra scheduler.Evan Cheng2010-06-121-6/+16
| | | | llvm-svn: 105862
* - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defsEvan Cheng2010-05-211-2/+2
| | | | | | | | | | that are aliases of the specified register. - Rename modifiesRegister to definesRegister since it's looking a def of the specific register or one of its super-registers. It's not looking for def of a sub-register or alias that could change the specified register. - Added modifiesRegister to look for defs of aliases. llvm-svn: 104377
* Remove dbg_value workaround and associated command line optionJim Grosbach2010-05-201-20/+0
| | | | llvm-svn: 104254
* Enable preserving debug information through post-RA schedulingJim Grosbach2010-05-191-1/+1
| | | | llvm-svn: 104175
* 80 column and trailing whitespace cleanupJim Grosbach2010-05-141-24/+25
| | | | llvm-svn: 103806
* add cmd line option to leave dbgvalues in during post-RA sceduling. UsefulJim Grosbach2010-05-141-5/+14
| | | | | | while debugging what's mishandled about them in the post-RA pass. llvm-svn: 103805
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-011-2/+2
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* As a temporary workaround for post-RA not handling DebugValue instructions,Bob Wilson2010-04-171-0/+11
| | | | | | | just remove them all. Radar 7873207 (working around the root problem of Radar 7759363). llvm-svn: 101604
* Remove a #include.Dan Gohman2010-04-121-1/+0
| | | | llvm-svn: 101043
* Fix some more places where dbg_value affected codegen.Dale Johannesen2010-03-051-0/+2
| | | | llvm-svn: 97765
* Change errs() to dbgs().David Greene2010-01-051-13/+13
| | | | llvm-svn: 92594
* <rdar://problem/7453528>. Track only physical registers that are valid for ↵David Goodwin2009-12-091-1/+2
| | | | | | the target. llvm-svn: 90970
* Don't hang on to pointers or references after vector::push_back.Jakob Stoklund Olesen2009-12-031-6/+3
| | | | | | | The MO reference to a MachineOperand can be invalidated by MachineInstr::addOperand. Don't even use it for debugging. llvm-svn: 90381
* Remove some old experimental code that is no longer needed. Remove ↵David Goodwin2009-11-201-112/+33
| | | | | | additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. llvm-svn: 89471
* Allow target to specify regclass for which antideps will only be broken ↵David Goodwin2009-11-131-3/+3
| | | | | | along the critical path. llvm-svn: 88682
* Rename registers to break output dependencies in addition to anti-dependencies.David Goodwin2009-11-121-3/+7
| | | | llvm-svn: 87015
* Fixed to address code review. No functional changes.David Goodwin2009-11-101-1/+1
| | | | llvm-svn: 86634
* Allow targets to specify register classes whose member registers should not ↵David Goodwin2009-11-101-2/+3
| | | | | | be renamed to break anti-dependencies. llvm-svn: 86628
* Break anti-dependencies using free registers in a round-robin manner to ↵David Goodwin2009-11-051-2/+4
| | | | | | avoid introducing new anti-dependencies. llvm-svn: 86098
* Do a scheduling pass ignoring anti-dependencies to identify candidate ↵David Goodwin2009-11-031-37/+112
| | | | | | registers that should be renamed. llvm-svn: 85939
* Make -print-machineinstrs more readable.Dan Gohman2009-10-311-2/+2
| | | | | | | | | | | | | | - Be consistent when referring to MachineBasicBlocks: BB#0. - Be consistent when referring to virtual registers: %reg1024. - Be consistent when referring to unknown physical registers: %physreg10. - Be consistent when referring to known physical registers: %RAX - Be consistent when referring to register 0: %reg0 - Be consistent when printing alignments: align=16 - Print jump table contents. - Don't print host addresses, in general. - and various other cleanups. llvm-svn: 85682
* Make AntiDepReg.h internal.David Goodwin2009-10-281-1/+1
| | | | llvm-svn: 85412
* Allow the aggressive anti-dep breaker to process the same region multiple ↵David Goodwin2009-10-261-6/+13
| | | | | | times. This is necessary because new anti-dependencies are exposed when "current" ones are broken. llvm-svn: 85166
* Define virtual destructor in *.cpp file.David Goodwin2009-10-261-0/+3
| | | | llvm-svn: 85146
* Add aggressive anti-dependence breaker. Currently it is not the default for ↵David Goodwin2009-10-261-3/+5
| | | | | | any target. Enable with -break-anti-dependencies=all. llvm-svn: 85145
* Break anti-dependence breaking out into its own class.David Goodwin2009-10-261-542/+43
| | | | llvm-svn: 85127
* Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky2009-10-251-1/+0
| | | | | | VISIBILITY_HIDDEN removal. llvm-svn: 85043
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-2/+2
| | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. llvm-svn: 85042
* Allow the target to select the level of anti-dependence breaking that should ↵David Goodwin2009-10-221-5/+16
| | | | | | be performed by the post-RA scheduler. The default is none. llvm-svn: 84911
* Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.Dan Gohman2009-10-211-489/+319
| | | | llvm-svn: 84727
* Respect src register allocation requirements when breaking ↵David Goodwin2009-10-201-17/+20
| | | | | | anti-dependencies. Remove some dead code. llvm-svn: 84691
* Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.David Goodwin2009-10-201-310/+477
| | | | llvm-svn: 84658
* Change createPostRAScheduler so it can be turned off at llc -O1.Evan Cheng2009-10-161-4/+6
| | | | llvm-svn: 84273
* If post-alloc scheduler is not enabled, it should return false, not true.Evan Cheng2009-10-161-3/+3
| | | | llvm-svn: 84248
* Add debugging output.David Goodwin2009-10-131-2/+12
| | | | llvm-svn: 84011
* Fix a missing initialization of PostRAScheduler's AA member.Dan Gohman2009-10-101-0/+2
| | | | llvm-svn: 83695
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-091-5/+13
| | | | | | | | | | | | | | is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. llvm-svn: 83687
* Fix a use-after-free in post-ra-scheduling.Benjamin Kramer2009-10-021-1/+3
| | | | | | | MI->addOperand invalidates references to it's operands, avoid touching the operand after a new one was added. llvm-svn: 83249
* All callee-saved registers are live-out of a return block.David Goodwin2009-10-011-18/+21
| | | | llvm-svn: 83223
* Remove neonfp attribute and instead set default based on CPU string. Add ↵David Goodwin2009-10-011-1/+1
| | | | | | -arm-use-neon-fp to override the default. llvm-svn: 83218
* Restore the -post-RA-scheduler flag as an override for the target ↵David Goodwin2009-10-011-5/+17
| | | | | | specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. llvm-svn: 83215
* Use MachineFrameInfo.getPristineRegs() to determine which callee-saved ↵David Goodwin2009-10-011-47/+30
| | | | | | registers are available for anti-dependency breaking. Some cleanup. llvm-svn: 83208
* Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not changeEvan Cheng2009-10-011-18/+55
| | | | | | operands of instructions with these properties while breaking anti-dep. llvm-svn: 83198
* Fix integer overflow in instruction scheduling. This can happen if we haveReid Kleckner2009-09-301-4/+4
| | | | | | | | | | basic blocks that are so long that their size overflows a short. Also assert that overflow does not happen in the future, as requested by Evan. This fixes PR4401. llvm-svn: 83159
* Remove -post-RA-schedule flag and add a TargetSubtarget method to enable ↵David Goodwin2009-09-301-0/+6
| | | | | | post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. llvm-svn: 83122
* Use KILL instead of IMPLICIT_DEF in LowerSubregs pass.Jakob Stoklund Olesen2009-09-281-3/+3
| | | | llvm-svn: 83007
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