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path: root/llvm/lib/CodeGen/PostRASchedulerList.cpp
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* If post-alloc scheduler is not enabled, it should return false, not true.Evan Cheng2009-10-161-3/+3
| | | | llvm-svn: 84248
* Add debugging output.David Goodwin2009-10-131-2/+12
| | | | llvm-svn: 84011
* Fix a missing initialization of PostRAScheduler's AA member.Dan Gohman2009-10-101-0/+2
| | | | llvm-svn: 83695
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-091-5/+13
| | | | | | | | | | | | | | is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. llvm-svn: 83687
* Fix a use-after-free in post-ra-scheduling.Benjamin Kramer2009-10-021-1/+3
| | | | | | | MI->addOperand invalidates references to it's operands, avoid touching the operand after a new one was added. llvm-svn: 83249
* All callee-saved registers are live-out of a return block.David Goodwin2009-10-011-18/+21
| | | | llvm-svn: 83223
* Remove neonfp attribute and instead set default based on CPU string. Add ↵David Goodwin2009-10-011-1/+1
| | | | | | -arm-use-neon-fp to override the default. llvm-svn: 83218
* Restore the -post-RA-scheduler flag as an override for the target ↵David Goodwin2009-10-011-5/+17
| | | | | | specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. llvm-svn: 83215
* Use MachineFrameInfo.getPristineRegs() to determine which callee-saved ↵David Goodwin2009-10-011-47/+30
| | | | | | registers are available for anti-dependency breaking. Some cleanup. llvm-svn: 83208
* Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not changeEvan Cheng2009-10-011-18/+55
| | | | | | operands of instructions with these properties while breaking anti-dep. llvm-svn: 83198
* Fix integer overflow in instruction scheduling. This can happen if we haveReid Kleckner2009-09-301-4/+4
| | | | | | | | | | basic blocks that are so long that their size overflows a short. Also assert that overflow does not happen in the future, as requested by Evan. This fixes PR4401. llvm-svn: 83159
* Remove -post-RA-schedule flag and add a TargetSubtarget method to enable ↵David Goodwin2009-09-301-0/+6
| | | | | | post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. llvm-svn: 83122
* Use KILL instead of IMPLICIT_DEF in LowerSubregs pass.Jakob Stoklund Olesen2009-09-281-3/+3
| | | | llvm-svn: 83007
* Fix bug in kill flag updating for post-register-allocation scheduling. When ↵David Goodwin2009-09-231-5/+48
| | | | | | the kill flag of a superreg needs to be cleared because there are one or more subregs live, we instead add implicit-defs of those subregs and leave the kill flag on the superreg. This allows us to end the live-range of the superreg without ending the live-ranges of the subregs. llvm-svn: 82629
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng2009-09-181-2/+2
| | | | | | | | sdisel will use to properly complete phi nodes. Not functionality change yet. llvm-svn: 82273
* It's a bool, so treat it like one. Fixes a MSVC warning.Benjamin Kramer2009-09-061-4/+4
| | | | llvm-svn: 81112
* Create our own block initializer for kill fixups as the scheduling one ↵David Goodwin2009-09-031-33/+63
| | | | | | wasn't doing the right thing. llvm-svn: 80958
* Add hidden flags to allow binary search of post-RA scheduling errors.David Goodwin2009-09-011-0/+21
| | | | llvm-svn: 80702
* Don't mark a register live at an undef use.David Goodwin2009-08-311-13/+8
| | | | llvm-svn: 80621
* Another stab at fixing up register kill flags after post-RA scheduling.David Goodwin2009-08-291-20/+63
| | | | llvm-svn: 80410
* Fixup register kills after scheduling.David Goodwin2009-08-251-21/+94
| | | | llvm-svn: 80002
* convert LoopInfo.h and GraphWriter.h to use raw_ostreamChris Lattner2009-08-231-2/+2
| | | | llvm-svn: 79836
* Fix counting of Post-RA scheduling stalls. Improve debug output.David Goodwin2009-08-121-14/+25
| | | | llvm-svn: 78843
* This logic was accidentally inverted in r78767.Dan Gohman2009-08-121-3/+3
| | | | llvm-svn: 78773
* Factor out the code for finding an available register for useDan Gohman2009-08-121-54/+70
| | | | | | in breaking an anti-dependence into a separate function. llvm-svn: 78767
* Use DEBUG macro for debug output.David Goodwin2009-08-111-11/+7
| | | | llvm-svn: 78694
* Add some debug output.David Goodwin2009-08-111-2/+14
| | | | llvm-svn: 78687
* Replace DOUT.David Goodwin2009-08-111-11/+12
| | | | llvm-svn: 78634
* Post RA scheduler changes. Introduce a hazard recognizer that uses the ↵David Goodwin2009-08-101-71/+21
| | | | | | target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. llvm-svn: 78563
* Use setPreservesAll and setPreservesCFG in CodeGen passes.Dan Gohman2009-07-311-0/+1
| | | | llvm-svn: 77754
* inline the global 'getInstrOperandRegClass' function into its callersChris Lattner2009-07-291-4/+7
| | | | | | now that TargetOperandInfo does the heavy lifting. llvm-svn: 77508
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-1/+2
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.Evan Cheng2009-05-051-12/+0
| | | | llvm-svn: 70950
* Fix pr3954. The register scavenger asserts for inline assembly withBob Wilson2009-04-091-1/+1
| | | | | | | | | | | | register destinations that are tied to source operands. The TargetInstrDescr::findTiedToSrcOperand method silently fails for inline assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very close to doing what is needed, so this revision makes a few changes to that method and also renames it to isRegTiedToUseOperand (for consistency with the very similar isRegTiedToDefOperand and because it handles both two-address instructions and inline assembly with tied registers). llvm-svn: 68714
* Add parentheses to pacify gcc-4.3.Duncan Sands2009-03-111-1/+1
| | | | llvm-svn: 66653
* Fix a post-RA scheduling liveness bug. When a basic block is beingDan Gohman2009-03-101-9/+22
| | | | | | | | | | | | | scheduled in multiple regions, liveness data used by the anti-dependence breaker is carried from one region to the next, however the information reflects the state of the instructions before scheduling. After scheduling, there may be new live range overlaps. Handle this by pessimizing the liveness data carried between regions to the point where it will be conservatively correct now matter how the earlier region is scheduled. This fixes a miscompilation in 176.gcc with the post-RA scheduler enabled. llvm-svn: 66558
* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-111-10/+28
| | | | | | | | | | | instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. llvm-svn: 64288
* Consider any instruction that modifies the stack pointer to beDan Gohman2009-02-101-0/+10
| | | | | | | | | a scheduling region boundary. This isn't necessary for correctness; it helps with compile time, as it avoids the need for data- and anti-dependencies from all spills and reloads on the stack-pointer modification. llvm-svn: 64255
* Factor out more code for computing register live-range informationforDan Gohman2009-02-101-191/+292
| | | | | | | | | | | scheduling, and generalize is so that preserves state across scheduling regions. This fixes incorrect live-range information around terminators and labels, which are effective region boundaries. In place of looking for terminators to anchor inter-block dependencies, introduce special entry and exit scheduling units for this purpose. llvm-svn: 64254
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-5/+4
| | | | llvm-svn: 63938
* Move ScheduleDAGInstrs.h to be a private header. Front-endsDan Gohman2009-02-061-1/+1
| | | | | | | | that used this header to select a scheduling policy should use SchedulerRegistry.h instead (llvm-gcc and clang were updated a while ago). llvm-svn: 63934
* Change the post-RA scheduler to iterate through theDan Gohman2009-02-031-9/+11
| | | | | | | | basic-block segments bottom-up instead of top down. This is the first step in a general restructuring of the way register liveness is tracked in the post-RA scheduler. llvm-svn: 63643
* Instead of adding dependence edges between terminator instructionsDan Gohman2009-01-161-2/+10
| | | | | | | | | | | | | | and every other instruction in their blocks to keep the terminator instructions at the end, teach the post-RA scheduler how to operate on ranges of instructions, and exclude terminators from the range of instructions that get scheduled. Also, exclude mid-block labels, such as EH_LABEL instructions, and schedule code before them separately from code after them. This fixes problems with the post-RA scheduler moving code past EH_LABELs. llvm-svn: 62366
* If an anti-dependence uses a non-allocatable register, set AntiDepRegDan Gohman2009-01-161-1/+3
| | | | | | | to 0, to ensure that the subsequent code doesn't try to break the dependence. llvm-svn: 62365
* Fix the check for an empty basic block to check for an empty SUnitsDan Gohman2009-01-161-2/+2
| | | | | | | | array instead, since this is what the scheduler actually cares about. And remove a check that is unnecessary, since it can assume that SUnits isn't empty. llvm-svn: 62362
* Fix a "comparison between signed and unsigned integer expressions"Dan Gohman2009-01-161-1/+1
| | | | | | warning. llvm-svn: 62327
* Initial hazard recognizer support in post-pass scheduling. This includesDan Gohman2009-01-161-8/+119
| | | | | | | a new toy hazard recognizier heuristic which attempts to direct the scheduler to avoid clumping large groups of loads or stores too densely. llvm-svn: 62291
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-11/+14
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-3/+0
| | | | llvm-svn: 61715
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