Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | Rename MachineVerifier pass to avoid command line collision. | Jakob Stoklund Olesen | 2009-05-17 | 1 | -1/+1 | |
| | | | | llvm-svn: 71987 | |||||
* | Verify that explicit definitions in the TargetInstrDesc are matched by | Jakob Stoklund Olesen | 2009-05-16 | 1 | -1/+12 | |
| | | | | | | explicit register define operands. llvm-svn: 71933 | |||||
* | Allow redefinition of reserved registers. | Jakob Stoklund Olesen | 2009-05-16 | 1 | -2/+3 | |
| | | | | llvm-svn: 71932 | |||||
* | Pacify gcc-4.3, which suggests explicit braces here | Duncan Sands | 2009-05-16 | 1 | -1/+2 | |
| | | | | | | to avoid an ambiguous else. llvm-svn: 71924 | |||||
* | Pass to verify generated machine code. | Jakob Stoklund Olesen | 2009-05-16 | 1 | -0/+677 | |
The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918 |