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path: root/llvm/lib/CodeGen/MachineScheduler.cpp
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* Pass LiveQueryResult by valueMatthias Braun2013-10-101-3/+5
| | | | | | | This makes the API a bit more natural to use and makes it easier to make LiveRanges implementation details private. llvm-svn: 192394
* Comment typo.Andrew Trick2013-09-241-1/+1
| | | | llvm-svn: 191312
* Allow subtarget selection of the default MachineScheduler and document the ↵Andrew Trick2013-09-201-12/+22
| | | | | | | | | | | interface. The global registry is used to allow command line override of the scheduler selection, but does not work well as the normal selection API. For example, the same LLVM process should be able to target multiple targets or subtargets. llvm-svn: 191071
* Rename ConvergingScheduler to GenericScheduler.Andrew Trick2013-09-191-63/+63
| | | | | | | | | | This was an experimental scheduler a year ago. It's now used by several subtargets, both in-order and out-of-order, and it is about to be enabled by default for x86 and armv7. It will be the new GenericScheduler for subtargets that don't provide their own SchedulingStrategy. llvm-svn: 191051
* Enable -misched-cyclicpath by default.Andrew Trick2013-09-091-1/+1
| | | | llvm-svn: 190367
* mi-sched: smooth out the cyclicpath heuristic.Andrew Trick2013-09-091-1/+4
| | | | | | | | | | | | | | | Arnold's idea. I generally try to avoid stateful heuristics because it can make debugging harder. However, we need a way to prevent the latency priority from dominating, and it somewhat makes sense to schedule aggressively for latency only within an issue group. Swift in particular likes this, and it doesn't hurt anyone else: | Benchmarks/MiBench/consumer-lame | 10.39% | | Benchmarks/Misc/himenobmtxpa | 9.63% | llvm-svn: 190360
* mi-sched: cleanup register pressure update, remove a FIXME.Andrew Trick2013-09-061-19/+26
| | | | llvm-svn: 190181
* mi-sched: improve regpressure tracing.Andrew Trick2013-09-061-2/+7
| | | | llvm-svn: 190180
* mi-sched: print tree size in -view-misched-dagsAndrew Trick2013-09-061-1/+5
| | | | llvm-svn: 190179
* mi-sched: register pressure update tracing.Andrew Trick2013-09-061-0/+4
| | | | llvm-svn: 190178
* mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.Andrew Trick2013-09-061-4/+4
| | | | | | The latency based scheduling could induce spills in some cases. llvm-svn: 190177
* Added MachineSchedPolicy.Andrew Trick2013-09-061-35/+51
| | | | | | | | Allow subtargets to customize the generic scheduling strategy. This is convenient for targets that don't need to add new heuristics by specializing the strategy. llvm-svn: 190176
* mi-sched: Force bottom up scheduling for generic targets.Andrew Trick2013-09-041-3/+23
| | | | | | | | | Fast register pressure tracking currently only takes effect during bottom up scheduling. Forcing this is a bit faster and simpler for targets that don't have many scheduling constraints and don't need top-down scheduling. llvm-svn: 190014
* comment typoAndrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189997
* Remove dead subtree limit code.Andrew Trick2013-09-041-9/+0
| | | | llvm-svn: 189995
* -view-misched-dags, better pruning.Andrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189994
* mi-sched: DEBUG cleanup, call tracePick for unidirectional scheduling.Andrew Trick2013-09-041-0/+2
| | | | llvm-svn: 189993
* 80 columnsAndrew Trick2013-09-041-2/+2
| | | | llvm-svn: 189992
* mi-sched: Suppress register pressure tracking when the scheduling window is ↵Andrew Trick2013-09-041-16/+29
| | | | | | | | | | too small. If the instruction window is < NumRegs/2, pressure tracking is not likely to be effective. The scheduler has to process a very large number of tiny blocks. We want this to be fast. llvm-svn: 189991
* mi-sched: Load clustering is a bit to expensive to enable unconditionally.Andrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189990
* mi-sched: Reuse an invalid HazardRecognizer to save compile time.Andrew Trick2013-09-041-6/+14
| | | | llvm-svn: 189989
* mi-sched: bypass heuristic checks when regpressure tracking is disabled.Andrew Trick2013-09-041-24/+29
| | | | llvm-svn: 189988
* Added -misched-regpressure option.Andrew Trick2013-09-041-13/+31
| | | | | | | | Register pressure tracking is half the complexity of the scheduler. It's useful to be able to turn it off for compile time and performance comparisons. llvm-svn: 189987
* Fix my previous checkin to updatePressureDiffs.Andrew Trick2013-08-311-4/+19
| | | | | | | | There was one case that we could hit a DebugValue where I didn't think to check. DebugValues are evil. No checkinable test case, sorry. It's an obvious fix. llvm-svn: 189717
* mi-sched: update PressureDiffs on-the-fly for liveness.Andrew Trick2013-08-301-5/+59
| | | | | | | This removes all expensive pressure tracking logic from the scheduling critical path of node comparison. llvm-svn: 189643
* mi-sched: improve the generic register pressure comparison.Andrew Trick2013-08-301-14/+12
| | | | | | | Only compare pressure within the same set. When multiple sets are affected, we prioritize the most constrained set. llvm-svn: 189641
* mi-sched: Precompute a PressureDiff for each instruction, adjust for ↵Andrew Trick2013-08-301-27/+51
| | | | | | | | | | | | | liveness later. Created SUPressureDiffs array to hold the per node PDiff computed during DAG building. Added a getUpwardPressureDelta API that will soon replace the old one. Compute PressureDelta here from the precomputed PressureDiffs. Updating for liveness will come next. llvm-svn: 189640
* comment typoAndrew Trick2013-08-301-1/+1
| | | | llvm-svn: 189635
* Comment and revise the cyclic critical path code.Andrew Trick2013-08-291-13/+116
| | | | | | This should be much more clear now. It's still disabled pending testing. llvm-svn: 189597
* Adds cyclic critical path computation and heuristics, temporarily disabled.Andrew Trick2013-08-231-21/+68
| | | | | | | | | | | Estimate the cyclic critical path within a single block loop. If the acyclic critical path is longer, then the loop will exhaust OOO resources after some number of iterations. If lag between the acyclic critical path and cyclic critical path is longer the the time it takes to issue those loop iterations, then aggressively schedule for latency. llvm-svn: 189120
* mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr ↵Andrew Trick2013-08-231-5/+7
| | | | | | | | | count. This fixes a pathological compile time problem with very large blocks and lots of scheduling boundaries. llvm-svn: 189116
* Confusing comment typo.Andrew Trick2013-08-071-1/+1
| | | | llvm-svn: 187895
* MI Sched: Track live-thru registers.Andrew Trick2013-07-301-2/+10
| | | | | | | | | | | When registers must be live throughout the scheduling region, increase the limit for the register class. Once we exceed the original limit, they will be spilled, and there's no point further reducing pressure. This isn't a perfect heuristics but avoids a situation where the scheduler could become trapped by trying to achieve the impossible. llvm-svn: 187436
* MI Sched fix: assert "Disconnected LRG within the scheduling region."Andrew Trick2013-07-301-0/+6
| | | | llvm-svn: 187435
* MI Sched: Register pressure heuristics.Andrew Trick2013-07-251-8/+32
| | | | | | Consider which set is being increased or decreased before comparing. llvm-svn: 187110
* Dump LIS before regalloc. MI sched changes them.Andrew Trick2013-07-251-2/+2
| | | | llvm-svn: 187107
* Fix uninitialized memory read found by MemorySanitizer: always set output ↵Alexey Samsonov2013-07-191-1/+1
| | | | | | parameter of ConvergingScheduler::SchedBoundary::getOtherResourceCount llvm-svn: 186658
* MI Sched: Update the way resources are tracked so the current heuristics ↵Andrew Trick2013-07-191-7/+5
| | | | | | make more sense. llvm-svn: 186632
* MI-Sched: cleanup DEBUG output.Andrew Trick2013-06-211-5/+6
| | | | llvm-svn: 184565
* MI-Sched: Adjust regpressure limits for reserved regs.Andrew Trick2013-06-211-2/+3
| | | | llvm-svn: 184564
* Give RegMax higher priority.Andrew Trick2013-06-171-9/+9
| | | | llvm-svn: 184133
* Remove compareRPDelta.Andrew Trick2013-06-171-37/+0
| | | | | | A complex, expensive heuristic with little value in the current design. llvm-svn: 184132
* MI-Sched: Remove another heuristic that is sensitive to queue order.Andrew Trick2013-06-171-6/+0
| | | | llvm-svn: 184130
* MI-Sched: Track multiple candidates with the same priority level.Andrew Trick2013-06-171-32/+25
| | | | | | | | This eliminates the MultiPressure scheduling "reason". It was sensitive to queue order. We don't like being sensitive to queue order. llvm-svn: 184129
* Missing NDEBUGs.Andrew Trick2013-06-151-0/+6
| | | | llvm-svn: 184039
* MI-Sched: heuristics using the new latency and machine model.Andrew Trick2013-06-151-234/+330
| | | | llvm-svn: 184038
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-13/+16
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
* MI-Sched: Rename IssueCount to CurrMOps.Andrew Trick2013-06-151-8/+8
| | | | | | | "Counts" refer to scaled resource counts within a region. CurrMOps is simply the number of micro-ops to be issue in the current cycle. llvm-svn: 184031
* MI-Sched: Remove the temporary EnableCopyConstrain flag.Andrew Trick2013-06-151-7/+1
| | | | llvm-svn: 184030
* MI-Sched: added tracking of dependent latency for better heuristics.Andrew Trick2013-06-151-13/+26
| | | | | | | | | | | | | | Heuristics compare the critical path in the scheduled code, called ExpectedLatency, with the latency of instructions remaining to be scheduled. There are two ways to look at remaining latency: (1) Dependent latency includes the latency between unscheduled and scheduled instructions. (2) Independent latency is simply the height (bottom-up) or depth (top-down) of instructions currently in the ready Q. llvm-svn: 184029
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