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* MI-Sched: DEBUG: print critical resource.Andrew Trick2013-06-151-0/+4
| | | | llvm-svn: 184028
* Move #include from .h to .cpp file.Jakub Staszak2013-06-141-0/+1
| | | | llvm-svn: 183960
* MI Sched: revert a minor heuristic that snuck in with -misched-vcopy.Andrew Trick2013-04-301-0/+6
| | | | | | I'll fix the heuristic in a general way in a follow-up commit. llvm-svn: 180815
* Fix for r180193 - MI Sched: eliminate local vreg.Andrew Trick2013-04-241-2/+6
| | | | | | | | | Fixes PR15838. Need to check for blocks with nothing but dbg.value. I'm not sure how to force this situation with a unit test. I tried to reduce the test case in PR15838 (1k lines of metadata) but gave up. llvm-svn: 180227
* MI Sched: eliminate local vreg copies.Andrew Trick2013-04-241-7/+194
| | | | | | | | | | | | | | | | For now, we just reschedule instructions that use the copied vregs and let regalloc elliminate it. I would really like to eliminate the copies on-the-fly during scheduling, but we need a complete implementation of repairIntervalsInRange() first. The general strategy is for the register coalescer to eliminate as many global copies as possible and shrink live ranges to be extended-basic-block local. The coalescer should not have to worry about resolving local copies (e.g. it shouldn't attemp to reorder instructions). The scheduler is a much better place to deal with local interference. The coalescer side of this equation needs work. llvm-svn: 180193
* MI Sched: regpressure tracing.Andrew Trick2013-04-241-0/+8
| | | | llvm-svn: 180191
* MI-Sched: DEBUG formatting.Andrew Trick2013-04-131-14/+22
| | | | llvm-svn: 179452
* MI-Sched: schedule physreg copies.Andrew Trick2013-04-131-1/+72
| | | | | | | | | | | The register allocator expects minimal physreg live ranges. Schedule physreg copies accordingly. This is slightly tricky when they occur in the middle of the scheduling region. For now, this is handled by rescheduling the copy when its associated instruction is scheduled. Eventually we may instead bundle them, but only if we can preserve the bundles as parallel copies during regalloc. llvm-svn: 179449
* RegisterPressure heuristics currently require signed comparisons.Andrew Trick2013-04-051-2/+2
| | | | llvm-svn: 178823
* Disable DFSResult for ConvergingScheduler.Andrew Trick2013-04-051-2/+0
| | | | | | | | For now, just save the compile time since the ConvergingScheduler heuristics don't use this analysis. We'll probably enable it later after compile-time investigation. llvm-svn: 178822
* MachineScheduler: format DEBUG output.Andrew Trick2013-04-051-22/+17
| | | | | | | I'm getting more serious about tuning and enabling on x86/ARM. Start by making the trace readable. llvm-svn: 178821
* Fix missing std::. Not sure how this compiles for anyone else.Matt Arsenault2013-03-211-1/+1
| | | | llvm-svn: 177620
* Cleanup #includes.Jakub Staszak2013-03-101-0/+2
| | | | llvm-svn: 176787
* Add -verify-misched option.Andrew Trick2013-03-081-0/+9
| | | | | | | | | | This verifies live intervals both before and after scheduling. It's useful for anyone hacking on live interval update. Note that we don't yet pass verification all the time. We don't yet handle updating nonallocatable live intervals perfectly. llvm-svn: 176685
* Use const reference instead of vector object when passing an argument toJakub Staszak2013-02-161-1/+1
| | | | | | updateScheduledPressure method. llvm-svn: 175362
* MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick2013-02-131-1/+6
| | | | llvm-svn: 175067
* MIsched: cleanup code. Use isBoundaryNode().Andrew Trick2013-01-291-2/+4
| | | | llvm-svn: 173775
* Use const reference instead of vector copying.Jakub Staszak2013-01-251-1/+2
| | | | llvm-svn: 173497
* MIsched: Print block name. No functionality.Andrew Trick2013-01-251-1/+2
| | | | llvm-svn: 173433
* MachineScheduler support for viewGraph.Andrew Trick2013-01-251-1/+88
| | | | llvm-svn: 173432
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-251-29/+33
| | | | | | | Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. llvm-svn: 173425
* MISched: Add SchedDFSResult to ScheduleDAGMI to formalize theAndrew Trick2013-01-251-25/+55
| | | | | | interface and allow other strategies to select it. llvm-svn: 173413
* MachineScheduler: enable biasCriticalPath for all DAGs.Andrew Trick2013-01-241-0/+4
| | | | llvm-svn: 173318
* Follow-up typo correction from building the wrong branch.Andrew Trick2013-01-111-2/+2
| | | | llvm-svn: 172224
* Fix typo from r170452. Affects -enable-misched heuristics.Andrew Trick2013-01-111-2/+2
| | | | llvm-svn: 172223
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-091-10/+2
| | | | | | | | | | This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. llvm-svn: 171946
* MISched: Cleanup, redundant statement.Andrew Trick2012-12-181-1/+0
| | | | llvm-svn: 170453
* MISched: Heuristics, compare latency more precisely. It matters more for ↵Andrew Trick2012-12-181-43/+38
| | | | | | some targets. llvm-svn: 170452
* MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to ↵Andrew Trick2012-12-181-3/+0
| | | | | | compute it. llvm-svn: 170451
* MISched: cleanup, use the proper iterator type.Andrew Trick2012-12-181-1/+1
| | | | llvm-svn: 170450
* MISched: minor improvement, initialize remaining resources before the first ↵Andrew Trick2012-12-181-0/+10
| | | | | | scheduling decision. llvm-svn: 170449
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-5/+4
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* misched: Fix RegisterPressureTracker handling of DebugVals.Andrew Trick2012-12-011-0/+4
| | | | | | | Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"). rdar://12790302. llvm-svn: 169072
* misched: fix RegionBegin when DebugValues get shuffled to the top.Andrew Trick2012-12-011-0/+2
| | | | | | | | assert (RemainingInstrs == 0 && "Instruction count mismatch!") rdar://12776937. llvm-svn: 169069
* misched: Recompute priority queue when DFSResults are updated.Benjamin Kramer2012-11-291-0/+2
| | | | | | | | This was found by MSVC10's STL debug mode on a test from the test suite. Sadly std::is_heap isn't standard so there is no way to assert this without writing our own heap verify, which looks like overkill to me. llvm-svn: 168885
* misched: Analysis that partitions the DAG into subtrees.Andrew Trick2012-11-281-15/+56
| | | | | | | | | | | This is a simple, cheap infrastructure for analyzing the shape of a DAG. It recognizes uniform DAGs that take the shape of bottom-up subtrees, such as the included matrix multiplication example. This is useful for heuristics that balance register pressure with ILP. Two canonical expressions of the heuristic are implemented in scheduling modes: -misched-ilpmin and -misched-ilpmax. llvm-svn: 168773
* misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.Andrew Trick2012-11-281-1/+1
| | | | llvm-svn: 168772
* misched: Debug output fix. Use an always valid iterator.Andrew Trick2012-11-281-1/+1
| | | | llvm-svn: 168767
* misched: Allow subtargets to enable misched and dependent options.Andrew Trick2012-11-131-2/+2
| | | | | | | | | | | | This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. llvm-svn: 167826
* misched: rename interfaceto avoid gcc warningsAndrew Trick2012-11-121-2/+1
| | | | llvm-svn: 167753
* misched: Target-independent support for MacroFusion.Andrew Trick2012-11-121-5/+61
| | | | | | | | | Uses the infrastructure from r167742 to support clustering instructure that the target processor can "fuse". e.g. cmp+jmp. Next step: target hook implementations with test cases, and enable. llvm-svn: 167744
* misched: Target-independent support for load/store clustering.Andrew Trick2012-11-121-12/+176
| | | | | | | | | | This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. llvm-svn: 167742
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-121-8/+18
| | | | | | | | This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. llvm-svn: 167738
* Silence GCC warning about falling off the end of a non-void function.Benjamin Kramer2012-11-091-0/+1
| | | | llvm-svn: 167618
* misched: Heuristics based on the machine model.Andrew Trick2012-11-071-146/+762
| | | | | | | | | | | | | | misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. llvm-svn: 167527
* misched: Rename RemainingCount to avoid confusion with remaining resources.Andrew Trick2012-11-061-6/+6
| | | | llvm-svn: 167443
* misched: Added handleMove support for updating all kill flags, not just for ↵Andrew Trick2012-10-161-1/+1
| | | | | | | | | allocatable regs. This is a medium term workaround until we have a more robust solution in the form of a register liveness utility for postRA passes. llvm-svn: 166001
* misched: ILP scheduler for experimental heuristics.Andrew Trick2012-10-151-20/+104
| | | | llvm-svn: 165950
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-101-10/+20
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
* misched: avoid scheduling an instruction twice.Andrew Trick2012-10-081-25/+29
| | | | llvm-svn: 165416
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