| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | MachineScheduler shouldn't use/preserve LiveDebugVariables. | Lang Hames | 2012-02-17 | 1 | -4/+0 |
| | | | | | llvm-svn: 150773 | ||||
| * | Disentangle moving a machine instr from updating LiveIntervals. | Lang Hames | 2012-02-15 | 1 | -1/+2 |
| | | | | | llvm-svn: 150552 | ||||
| * | RegAlloc superpass: includes phi elimination, coalescing, and scheduling. | Andrew Trick | 2012-02-10 | 1 | -8/+0 |
| | | | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226 | ||||
| * | comment | Andrew Trick | 2012-02-09 | 1 | -1/+1 |
| | | | | | llvm-svn: 150121 | ||||
| * | misched: bug in debug output. | Andrew Trick | 2012-02-08 | 1 | -2/+4 |
| | | | | | llvm-svn: 150043 | ||||
| * | stale comment | Andrew Trick | 2012-02-08 | 1 | -2/+0 |
| | | | | | llvm-svn: 150041 | ||||
| * | Add a "moveInstr" method to LiveIntervals. This can be used to move instructions | Lang Hames | 2012-01-27 | 1 | -1/+3 |
| | | | | | | | | | | around within a basic block while maintaining live-intervals. Updated ScheduleTopDownLive in MachineScheduler.cpp to use the moveInstr API when reordering MIs. llvm-svn: 149147 | ||||
| * | misched: Inital interface and implementation for ScheduleTopDownLive and ↵ | Andrew Trick | 2012-01-17 | 1 | -17/+130 |
| | | | | | | | ShuffleInstructions. llvm-svn: 148291 | ||||
| * | Renamed MachineScheduler to ScheduleTopDownLive. | Andrew Trick | 2012-01-17 | 1 | -47/+59 |
| | | | | | | | Responding to code review. llvm-svn: 148290 | ||||
| * | misched: Initial code for building an MI level scheduling DAG | Andrew Trick | 2012-01-14 | 1 | -10/+14 |
| | | | | | llvm-svn: 148174 | ||||
| * | misched: Added ScheduleDAGInstrs::IsPostRA | Andrew Trick | 2012-01-14 | 1 | -2/+2 |
| | | | | | llvm-svn: 148172 | ||||
| * | misched: Invoke the DAG builder on each sequence of schedulable instructions. | Andrew Trick | 2012-01-14 | 1 | -6/+31 |
| | | | | | llvm-svn: 148171 | ||||
| * | Move things around to make the file navigable, even though it will probably ↵ | Andrew Trick | 2012-01-14 | 1 | -19/+32 |
| | | | | | | | be split up later. llvm-svn: 148170 | ||||
| * | Added the MachineSchedulerPass skeleton. | Andrew Trick | 2012-01-13 | 1 | -0/+233 |
| llvm-svn: 148105 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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