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path: root/llvm/lib/CodeGen/MachineScheduler.cpp
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* [C++11] Convert sort predicates into lambdas.Benjamin Kramer2014-03-071-11/+5
| | | | | | No functionality change. llvm-svn: 203288
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-071-15/+15
| | | | | | class. llvm-svn: 203220
* Replace OwningPtr<T> with std::unique_ptr<T>.Ahmed Charles2014-03-061-3/+2
| | | | | | | | | | This compiles with no changes to clang/lld/lldb with MSVC and includes overloads to various functions which are used by those projects and llvm which have OwningPtr's as parameters. This should allow out of tree projects some time to move. There are also no changes to libs/Target, which should help out of tree targets have time to move, if necessary. llvm-svn: 203083
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-11/+10
| | | | | | Remove the old functions. llvm-svn: 202636
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-021-17/+17
| | | | llvm-svn: 202621
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* Reformat a loop for basic hygeine. Self review.Andrew Trick2014-01-221-5/+5
| | | | llvm-svn: 199788
* Fix PR18572 - llc crash during GenericScheduler::initPolicy().Andrew Trick2014-01-211-4/+10
| | | | | | | Generalized the heuristic that looks at the (very rough) size of the register file before enabling regpressure tracking. llvm-svn: 199766
* CodeGen: silence a C++11 feature warningSaleem Abdulrasool2013-12-281-1/+1
| | | | llvm-svn: 198133
* Uninitialized variable (in never taken path) after factoring.Andrew Trick2013-12-281-1/+1
| | | | llvm-svn: 198131
* Added debugging options: -misched-only-func/blockAndrew Trick2013-12-281-0/+13
| | | | llvm-svn: 198124
* Add a PostMachineScheduler pass with generic implementation.Andrew Trick2013-12-281-284/+522
| | | | | | | | | | | | | | | | | | | | | | | | | PostGenericScheduler uses either the new machine model or the hazard checker for top-down scheduling. Most of the infrastructure for PreRA machine scheduling is reused. With a some tuning, this should allow MachineScheduler to be default for all ARM targets, including cortex-A9, using the new machine model. Likewise, with additional tuning, it should be able to replace PostRAScheduler for all targets. The PostMachineScheduler pass does not currently run the AntiDepBreaker. There is less need for it on targets that are already running preRA MachineScheduler. I want to prove it's necessary before committing to the maintenance burden. The PostMachineScheduler also currently removes kill flags and adds them all back later. This is a bit ridiculous. I'd prefer passes to directly use a liveness utility than rely on flags. A test case that enables this scheduler will be included in a subsequent checkin that updates the A9 model. llvm-svn: 198122
* Stub out a PostMachineScheduler pass.Andrew Trick2013-12-281-0/+69
| | | | | | Placeholder and boilerplate for a PostRA MachineScheduler pass. llvm-svn: 198120
* Factor MI-Sched in preparation for post-ra scheduling support.Andrew Trick2013-12-281-186/+308
| | | | | | | | Factor the MachineFunctionPass into MachineSchedulerBase. Split the DAG class into ScheduleDAGMI and SchedulerDAGMILive. llvm-svn: 198119
* Factor out the SchedRemainder/SchedBoundary from GenericScheduler strategy.Andrew Trick2013-12-071-616/+440
| | | | | | | | | | | | | These helper classes take care of the book-keeping the drives the GenericScheduler heuristics. It is likely that developers writing target-specific schedulers that work similarly to GenericScheduler will want to use these helpers too. The immediate goal is to develop a GenericPostScheduler that can run in place of the old PostRAScheduler, but will use the new machine model. No functionality change intended. llvm-svn: 196643
* comment grammarAndrew Trick2013-12-061-1/+1
| | | | llvm-svn: 196585
* Fix bug introduced in r196517.Daniel Jasper2013-12-061-2/+3
| | | | | | | | | | Not only does it trigger -Wparentheses, I think the assert actually relies on incorrect operator precedence. Also, the grammar as questionable, but I might not know enough about the problem at hand. llvm-svn: 196567
* MI-Sched: Model "reserved" processor resources.Andrew Trick2013-12-051-19/+74
| | | | | | | | | | | | | | | | | | | This allows a target to use MI-Sched as an in-order scheduler that will model strict resource conflicts without defining a processor itinerary. Instead, the target can now use the new per-operand machine model and define in-order resources with BufferSize=0. For example, this would allow restricting the type of operations that can be formed into a dispatch group. (Normally NumMicroOps is sufficient to enforce dispatch groups). If the intent is to model latency in in-order pipeline, as opposed to resource conflicts, then a resource with BufferSize=1 should be defined instead. This feature is only casually tested as there are no in-tree targets using it yet. However, Hal will be experimenting with POWER7. llvm-svn: 196517
* MI-Sched: handle latency of in-order operations with the new machine model.Andrew Trick2013-12-051-5/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The per-operand machine model allows the target to define "unbuffered" processor resources. This change is a quick, cheap way to model stalls caused by the latency of operations that use such resources. This only applies when the processor's micro-op buffer size is non-zero (Out-of-Order). We can't precisely model in-order stalls during out-of-order execution, but this is an easy and effective heuristic. It benefits cortex-a9 scheduling when using the new machine model, which is not yet on by default. MI-Sched for armv7 was evaluated on Swift (and only not enabled because of a performance bug related to predication). However, we never evaluated Cortex-A9 performance on MI-Sched in its current form. This change adds MI-Sched functionality to reach performance goals on A9. The only remaining change is to allow MI-Sched to run as a PostRA pass. I evaluated performance using a set of options to estimate the performance impact once MI sched is default on armv7: -mcpu=cortex-a9 -disable-post-ra -misched-bench -scheditins=false For a simple saxpy loop I see a 1.7x speedup. Here are the llvm-testsuite results: (min run time over 2 runs, filtering tiny changes) Speedups: | Benchmarks/BenchmarkGame/recursive | 52.39% | | Benchmarks/VersaBench/beamformer | 20.80% | | Benchmarks/Misc/pi | 19.97% | | Benchmarks/Misc/mandel-2 | 19.95% | | SPEC/CFP2000/188.ammp | 18.72% | | Benchmarks/McCat/08-main/main | 18.58% | | Benchmarks/Misc-C++/Large/sphereflake | 18.46% | | Benchmarks/Olden/power | 17.11% | | Benchmarks/Misc-C++/mandel-text | 16.47% | | Benchmarks/Misc/oourafft | 15.94% | | Benchmarks/Misc/flops-7 | 14.99% | | Benchmarks/FreeBench/distray | 14.26% | | SPEC/CFP2006/470.lbm | 14.00% | | mediabench/mpeg2/mpeg2dec/mpeg2decode | 12.28% | | Benchmarks/SmallPT/smallpt | 10.36% | | Benchmarks/Misc-C++/Large/ray | 8.97% | | Benchmarks/Misc/fp-convert | 8.75% | | Benchmarks/Olden/perimeter | 7.10% | | Benchmarks/Bullet/bullet | 7.03% | | Benchmarks/Misc/mandel | 6.75% | | Benchmarks/Olden/voronoi | 6.26% | | Benchmarks/Misc/flops-8 | 5.77% | | Benchmarks/Misc/matmul_f64_4x4 | 5.19% | | Benchmarks/MiBench/security-rijndael | 5.15% | | Benchmarks/Misc/flops-6 | 5.10% | | Benchmarks/Olden/tsp | 4.46% | | Benchmarks/MiBench/consumer-lame | 4.28% | | Benchmarks/Misc/flops-5 | 4.27% | | Benchmarks/mafft/pairlocalalign | 4.19% | | Benchmarks/Misc/himenobmtxpa | 4.07% | | Benchmarks/Misc/lowercase | 4.06% | | SPEC/CFP2006/433.milc | 3.99% | | Benchmarks/tramp3d-v4 | 3.79% | | Benchmarks/FreeBench/pifft | 3.66% | | Benchmarks/Ptrdist/ks | 3.21% | | Benchmarks/Adobe-C++/loop_unroll | 3.12% | | SPEC/CINT2000/175.vpr | 3.12% | | Benchmarks/nbench | 2.98% | | SPEC/CFP2000/183.equake | 2.91% | | Benchmarks/Misc/perlin | 2.85% | | Benchmarks/Misc/flops-1 | 2.82% | | Benchmarks/Misc-C++-EH/spirit | 2.80% | | Benchmarks/Misc/flops-2 | 2.77% | | Benchmarks/NPB-serial/is | 2.42% | | Benchmarks/ASC_Sequoia/CrystalMk | 2.33% | | Benchmarks/BenchmarkGame/n-body | 2.28% | | Benchmarks/SciMark2-C/scimark2 | 2.27% | | Benchmarks/Olden/bh | 2.03% | | skidmarks10/skidmarks | 1.81% | | Benchmarks/Misc/flops | 1.72% | Slowdowns: | Benchmarks/llubenchmark/llu | -14.14% | | Benchmarks/Polybench/stencils/seidel-2d | -5.67% | | Benchmarks/Adobe-C++/functionobjects | -5.25% | | Benchmarks/Misc-C++/oopack_v1p8 | -5.00% | | Benchmarks/Shootout/hash | -2.35% | | Benchmarks/Prolangs-C++/ocean | -2.01% | | Benchmarks/Polybench/medley/floyd-warshall | -1.98% | | Polybench/linear-algebra/kernels/3mm | -1.95% | | Benchmarks/McCat/09-vor/vor | -1.68% | llvm-svn: 196516
* comment typo and reformatAndrew Trick2013-12-051-6/+6
| | | | llvm-svn: 196513
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-0/+4
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-4/+0
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-0/+4
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Pass LiveQueryResult by valueMatthias Braun2013-10-101-3/+5
| | | | | | | This makes the API a bit more natural to use and makes it easier to make LiveRanges implementation details private. llvm-svn: 192394
* Comment typo.Andrew Trick2013-09-241-1/+1
| | | | llvm-svn: 191312
* Allow subtarget selection of the default MachineScheduler and document the ↵Andrew Trick2013-09-201-12/+22
| | | | | | | | | | | interface. The global registry is used to allow command line override of the scheduler selection, but does not work well as the normal selection API. For example, the same LLVM process should be able to target multiple targets or subtargets. llvm-svn: 191071
* Rename ConvergingScheduler to GenericScheduler.Andrew Trick2013-09-191-63/+63
| | | | | | | | | | This was an experimental scheduler a year ago. It's now used by several subtargets, both in-order and out-of-order, and it is about to be enabled by default for x86 and armv7. It will be the new GenericScheduler for subtargets that don't provide their own SchedulingStrategy. llvm-svn: 191051
* Enable -misched-cyclicpath by default.Andrew Trick2013-09-091-1/+1
| | | | llvm-svn: 190367
* mi-sched: smooth out the cyclicpath heuristic.Andrew Trick2013-09-091-1/+4
| | | | | | | | | | | | | | | Arnold's idea. I generally try to avoid stateful heuristics because it can make debugging harder. However, we need a way to prevent the latency priority from dominating, and it somewhat makes sense to schedule aggressively for latency only within an issue group. Swift in particular likes this, and it doesn't hurt anyone else: | Benchmarks/MiBench/consumer-lame | 10.39% | | Benchmarks/Misc/himenobmtxpa | 9.63% | llvm-svn: 190360
* mi-sched: cleanup register pressure update, remove a FIXME.Andrew Trick2013-09-061-19/+26
| | | | llvm-svn: 190181
* mi-sched: improve regpressure tracing.Andrew Trick2013-09-061-2/+7
| | | | llvm-svn: 190180
* mi-sched: print tree size in -view-misched-dagsAndrew Trick2013-09-061-1/+5
| | | | llvm-svn: 190179
* mi-sched: register pressure update tracing.Andrew Trick2013-09-061-0/+4
| | | | llvm-svn: 190178
* mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.Andrew Trick2013-09-061-4/+4
| | | | | | The latency based scheduling could induce spills in some cases. llvm-svn: 190177
* Added MachineSchedPolicy.Andrew Trick2013-09-061-35/+51
| | | | | | | | Allow subtargets to customize the generic scheduling strategy. This is convenient for targets that don't need to add new heuristics by specializing the strategy. llvm-svn: 190176
* mi-sched: Force bottom up scheduling for generic targets.Andrew Trick2013-09-041-3/+23
| | | | | | | | | Fast register pressure tracking currently only takes effect during bottom up scheduling. Forcing this is a bit faster and simpler for targets that don't have many scheduling constraints and don't need top-down scheduling. llvm-svn: 190014
* comment typoAndrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189997
* Remove dead subtree limit code.Andrew Trick2013-09-041-9/+0
| | | | llvm-svn: 189995
* -view-misched-dags, better pruning.Andrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189994
* mi-sched: DEBUG cleanup, call tracePick for unidirectional scheduling.Andrew Trick2013-09-041-0/+2
| | | | llvm-svn: 189993
* 80 columnsAndrew Trick2013-09-041-2/+2
| | | | llvm-svn: 189992
* mi-sched: Suppress register pressure tracking when the scheduling window is ↵Andrew Trick2013-09-041-16/+29
| | | | | | | | | | too small. If the instruction window is < NumRegs/2, pressure tracking is not likely to be effective. The scheduler has to process a very large number of tiny blocks. We want this to be fast. llvm-svn: 189991
* mi-sched: Load clustering is a bit to expensive to enable unconditionally.Andrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189990
* mi-sched: Reuse an invalid HazardRecognizer to save compile time.Andrew Trick2013-09-041-6/+14
| | | | llvm-svn: 189989
* mi-sched: bypass heuristic checks when regpressure tracking is disabled.Andrew Trick2013-09-041-24/+29
| | | | llvm-svn: 189988
* Added -misched-regpressure option.Andrew Trick2013-09-041-13/+31
| | | | | | | | Register pressure tracking is half the complexity of the scheduler. It's useful to be able to turn it off for compile time and performance comparisons. llvm-svn: 189987
* Fix my previous checkin to updatePressureDiffs.Andrew Trick2013-08-311-4/+19
| | | | | | | | There was one case that we could hit a DebugValue where I didn't think to check. DebugValues are evil. No checkinable test case, sorry. It's an obvious fix. llvm-svn: 189717
* mi-sched: update PressureDiffs on-the-fly for liveness.Andrew Trick2013-08-301-5/+59
| | | | | | | This removes all expensive pressure tracking logic from the scheduling critical path of node comparison. llvm-svn: 189643
* mi-sched: improve the generic register pressure comparison.Andrew Trick2013-08-301-14/+12
| | | | | | | Only compare pressure within the same set. When multiple sets are affected, we prioritize the most constrained set. llvm-svn: 189641
* mi-sched: Precompute a PressureDiff for each instruction, adjust for ↵Andrew Trick2013-08-301-27/+51
| | | | | | | | | | | | | liveness later. Created SUPressureDiffs array to hold the per node PDiff computed during DAG building. Added a getUpwardPressureDelta API that will soon replace the old one. Compute PressureDelta here from the precomputed PressureDiffs. Updating for liveness will come next. llvm-svn: 189640
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