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* MachineScheduler/ScheduleDAG: Add support to skipping a node.Matthias Braun2016-11-111-0/+7
| | | | | | | | | | | The DAG mutators in the scheduler cannot really remove DAG nodes as additional anlysis information such as ScheduleDAGToplogicalSort are already computed at this point and rely on a fixed number of DAG nodes. Alleviate the missing removal with a new flag: Setting the new skip flag on a node ignores it during scheduling. llvm-svn: 286655
* ScheduleDAGInstrs: Move VRegUses to ScheduleDAGMILive; NFCIMatthias Braun2016-11-111-0/+43
| | | | | | | | | | | | | Push VRegUses/collectVRegUses() down the class hierarchy towards its only user ScheduleDAGMILive. NFCI: The initialization of the map happens at a later point but that should not matter. This is in preparation to allow DAG mutators to merge nodes, which relies on this map getting computed later. llvm-svn: 286654
* MachineScheduler: Dump EntrySU/ExitSU if possibleMatthias Braun2016-11-111-2/+12
| | | | llvm-svn: 286653
* ScheduleDAGInstrs: Add condjump deps to addSchedBarrierDeps()Matthias Braun2016-11-111-30/+20
| | | | | | | | | | | | | | | addSchedBarrierDeps() is supposed to add use operands to the ExitSU node. The current implementation adds uses for calls/barrier instruction and the MBB live-outs in all other cases. The use operands of conditional jump instructions were missed. Also added code to macrofusion to set the latencies between nodes to zero to avoid problems with the fusing nodes lingering around in the pending list now. Differential Revision: https://reviews.llvm.org/D25140 llvm-svn: 286544
* [MachineScheduler] Comments fixing.Jonas Paulsson2016-11-091-1/+2
| | | | | | | | The name/comment of the third argument to the ScheduleDAGMI constructor is RemoveKillFlags and not IsPostRA. Only the comments are changed. Review: A Trick llvm-svn: 286350
* Comment rewording in MachineScheduler.cpp.Jonas Paulsson2016-11-041-3/+2
| | | | | Author: A Trick llvm-svn: 285991
* Fix differences in codegen between Linux and Windows toolchainsMandeep Singh Grang2016-10-181-1/+2
| | | | | | | | | | | | | | | | | Summary: There are differences in codegen between Linux and Windows due to: 1. Using std::sort which uses quicksort which is a non-stable sort. 2. Iterating over Set data structure where the iteration order is non deterministic. Reviewers: arsenm, grosbach, junbuml, zinob, MatzeB Subscribers: MatzeB, wdng Differential Revision: https://reviews.llvm.org/D25695 llvm-svn: 284441
* MachineScheduler: Slightly simplify release nodeMatthias Braun2016-09-221-14/+0
| | | | llvm-svn: 282201
* MachineScheduler: Remove ineffective heuristic; NFCMatthias Braun2016-09-221-11/+0
| | | | | | | | | Currently all nodes get added to the NextSU list when they are released, so any candidate must be in that list, making the heuristic ineffective. Remove it for now, we can add it back later in a working fashion if necessary. llvm-svn: 282200
* MachineScheduler: Add constructor functions for the DAGMutationsTom Stellard2016-08-191-4/+40
| | | | | | | | | | | | Summary: This way they can be re-used by target-specific schedulers. Reviewers: atrick, MatzeB, kparzysz Subscribers: kparzysz, llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D23678 llvm-svn: 279305
* CodeGen: Avoid dereferencing end() when unconstifying iteratorsDuncan P. N. Exon Smith2016-08-161-8/+4
| | | | | | | | Rather than doing a funny dance that relies on dereferencing end() not crashing, add some API to MachineInstrBundleIterator to get a non-const version of the iterator. llvm-svn: 278870
* CodeGen: Avoid dereferencing end() in MachineSchedulerDuncan P. N. Exon Smith2016-08-111-2/+3
| | | | | | | | | | | | | | | | Check MachineInstr::isDebugValue for the same instruction as we're calling isSchedBoundary, avoiding the possibility of dereferencing end(). This is a functionality change even when I!=end(). Matthias had a look and agrees this is the right resolution (as opposed to checking for end()). This is triggered by a huge number of tests, but they happen to magically pass right now. I found this because WIP patches for PR26753 convert them into crashes. llvm-svn: 278394
* Target: Remove unused arguments from overrideSchedPolicy, NFCDuncan P. N. Exon Smith2016-07-011-2/+1
| | | | | | | | | | TargetSubtargetInfo::overrideSchedPolicy takes two MachineInstr* arguments (begin and end) that invite implicit conversions from MachineInstrBundleIterator. One option would be to change their type to an iterator, but since they don't seem to have been used since the API was added in 2010, I'm deleting the dead code. llvm-svn: 274304
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* MachineScheduler: Remember top/bottom choice in bidirectional schedulingMatthias Braun2016-06-251-9/+50
| | | | | | | | | | | | | Remember the last choice for the top/bottom scheduling boundary in bidirectional scheduling mode. The top choice should not change if we schedule at the bottom and vice versa. This allows us to improve compiletime: We only recalculate the best pick for one border and re-use the cached top-pick from the other border. Differential Revision: http://reviews.llvm.org/D19350 llvm-svn: 273766
* MachineScheduler: Fully compare top/bottom candidatesMatthias Braun2016-06-251-99/+103
| | | | | | | | | | In bidirectional scheduling this gives more stable results than just comparing the "reason" fields of the top/bottom node because the reason field may be higher depending on what other nodes are in the queue. Differential Revision: http://reviews.llvm.org/D19401 llvm-svn: 273755
* MachineScheduler: Followup to debug message changesMatthias Braun2016-06-231-1/+0
| | | | | | | Do not dump intermediate state of the pending queue anymore now that we always dump the final state before picking. llvm-svn: 273618
* MachineScheduler: Improve debug messagesMatthias Braun2016-06-231-7/+7
| | | | | | | Consistenly display available and pending queues immediately before the scheduling choice is done. llvm-svn: 273615
* CodeGen: Refactor renameDisconnectedComponents() as a passMatthias Braun2016-05-311-10/+2
| | | | | | | | | | | | | | | | | | Refactor LiveIntervals::renameDisconnectedComponents() to be a pass. Also change the name to "RenameIndependentSubregs": - renameDisconnectedComponents() worked on a MachineFunction at a time so it is a natural candidate for a machine function pass. - The algorithm is testable with a .mir test now. - This also fixes a problem where the lazy renaming as part of the MachineScheduler introduced IMPLICIT_DEF instructions after the number of a nodes in a region were counted leading to a mismatch. Differential Revision: http://reviews.llvm.org/D20507 llvm-svn: 271345
* MachineScheduler: Introduce ONLY1 reason to improve debug outputMatthias Braun2016-05-271-6/+13
| | | | llvm-svn: 271058
* LiveIntervalAnalysis: Fix missing defs in renameDisconnectedComponents().Matthias Braun2016-05-201-7/+2
| | | | | | | | | | | | | | Fix renameDisconnectedComponents() creating vreg uses that can be reached from function begin withouthaving a definition (or explicit live-in). Fix this by inserting IMPLICIT_DEF instruction before control-flow joins as necessary. Removes an assert from MachineScheduler because we may now get additional IMPLICIT_DEF when preparing the scheduling policy. This fixes the underlying problem of http://llvm.org/PR27705 llvm-svn: 270259
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-101-0/+1
| | | | | | | | Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it. llvm-svn: 269011
* Reset the TopRPTracker's position in ScheduleDAGMILive::initQueuesKrzysztof Parzyszek2016-04-281-5/+11
| | | | | | | | | | | | | | | | | | | ScheduleDAGMI::initQueues changes the RegionBegin to the first non-debug instruction. Since it does not track register pressure, it does not affect any RP trackers. ScheduleDAGMILive inherits initQueues from ScheduleDAGMI, and it does reset the TopTPTracker in its schedule method. Any derived, target-specific scheduler will need to do it as well, but the TopRPTracker is only exposed as a "const" object to derived classes. Without the ability to modify the tracker directly, this leaves a derived scheduler with a potential of having the TopRPTracker out-of-sync with the CurrentTop. The symptom of the problem: void llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit *, bool): Assertion `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. Differential Revision: http://reviews.llvm.org/D19438 llvm-svn: 267918
* Re-commit optimization bisect support (r267022) without new pass manager ↵Andrew Kaylor2016-04-221-2/+2
| | | | | | | | | | support. The original commit was reverted because of a buildbot problem with LazyCallGraph::SCC handling (not related to the OptBisect handling). Differential Revision: http://reviews.llvm.org/D19172 llvm-svn: 267231
* MachineScheduler: Move code to initialize a Candidate out of tryCandidate(); NFCMatthias Braun2016-04-221-33/+33
| | | | llvm-svn: 267191
* MachineScheduler: Limit the size of the ready list.Matthias Braun2016-04-221-1/+10
| | | | | | | | | Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists. Differential Revision: http://reviews.llvm.org/D19349 llvm-svn: 267189
* Revert "Initial implementation of optimization bisect support."Vedant Kumar2016-04-221-2/+2
| | | | | | | | This reverts commit r267022, due to an ASan failure: http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/1549 llvm-svn: 267115
* Initial implementation of optimization bisect support.Andrew Kaylor2016-04-211-2/+2
| | | | | | | | | | | | This patch implements a optimization bisect feature, which will allow optimizations to be selectively disabled at compile time in order to track down test failures that are caused by incorrect optimizations. The bisection is enabled using a new command line option (-opt-bisect-limit). Individual passes that may be skipped call the OptBisect object (via an LLVMContext) to see if they should be skipped based on the bisect limit. A finer level of control (disabling individual transformations) can be managed through an addition OptBisect method, but this is not yet used. The skip checking in this implementation is based on (and replaces) the skipOptnoneFunction check. Where that check was being called, a new call has been inserted in its place which checks the bisect limit and the optnone attribute. A new function call has been added for module and SCC passes that behaves in a similar way. Differential Revision: http://reviews.llvm.org/D19172 llvm-svn: 267022
* MachineSched: Cleanup; NFCMatthias Braun2016-04-211-32/+16
| | | | llvm-svn: 266946
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [MachineScheduler]Add support for store clusteringJun Bum Lim2016-04-151-35/+60
| | | | | | | | | | | | Perform store clustering just like load clustering. This change add StoreClusterMutation in machine-scheduler. To control StoreClusterMutation, added enableClusterStores() in TargetInstrInfo.h. This is enabled only on AArch64 for now. This change also add support for unscaled stores which were not handled in getMemOpBaseRegImmOfs(). llvm-svn: 266437
* MachineScheduler: Ignore COPYs with undef/dead op in CopyConstrain mutation.Matthias Braun2016-04-041-4/+6
| | | | | | | | There is no problem with the code today, but the fix will avoid a crash in test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll once the DetectDeadLanes pass is added. llvm-svn: 265351
* [misched] Fix a truncation issue from r263021.Chad Rosier2016-03-111-1/+1
| | | | | | | | | The truncation was causing the sorting algorithm to behave oddly when comparing positive and negative offsets. Fortunately, this doesn't currently happen in practice and was exposed by a WIP. Thus, I can't test this change now, but the follow on patch will. llvm-svn: 263255
* [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.Chad Rosier2016-03-091-2/+2
| | | | | | http://reviews.llvm.org/D17967 llvm-svn: 263021
* Add DAG mutation interface to the post-RA schedulerKrzysztof Parzyszek2016-03-051-6/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D17868 llvm-svn: 262774
* CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-271-1/+1
| | | | | | These parameters aren't expected to be null, so take them by reference. llvm-svn: 262151
* CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFCDuncan P. N. Exon Smith2016-02-271-9/+8
| | | | | | | | | | | | | | Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
* MachineScheduler: Add a command line option to disable post scheduler.Chad Rosier2016-01-201-1/+9
| | | | llvm-svn: 258364
* MachineScheduler: Honor optnone functions in the pre-ra scheduler.Chad Rosier2016-01-201-0/+3
| | | | llvm-svn: 258363
* MachineScheduler: Allow independent scheduling of sub register defsMatthias Braun2016-01-201-43/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Note that this is disabled by default and still requires a patch to handleMove() which is not upstreamed yet. If the TrackLaneMasks policy/strategy is enabled the MachineScheduler will build a schedule graph where definitions of independent subregisters are no longer serialised. Implementation comments: - Without lane mask tracking a sub register def also counts as a use (except for the first one with the read-undef flag set), with lane mask tracking enabled this is no longer the case. - Pressure Diffs where previously maintained per definition of a vreg with the help of the SSA information contained in the LiveIntervals. With lanemask tracking enabled we cannot do this anymore and instead change the pressure diffs for all uses of the vreg as it becomes live/dead. For this changed style to work correctly we ignore uses of instructions that define the same register again: They won't affect register pressure. - With lanemask tracking we remove all read-undef flags from sub register defs when building the graph and re-add them later when all vreg lanes have become dead. Differential Revision: http://reviews.llvm.org/D14969 llvm-svn: 258259
* RegisterPressure: Make liveness tracking subregister awareMatthias Braun2016-01-201-12/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D14968 llvm-svn: 258258
* MachineScheduler: Add a target hook for deciding which RegPressure sets toTom Stellard2015-12-161-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | increase Summary: This patch adds a function called getRegPressureSetScore() to TargetRegisterInfo. The MachineScheduler uses this when comparing instruction that increase the register pressure of different sets to determine which set is safer to increase. This hook is useful for GPU targets where the number of registers in the class is not the best metric for determing which presser set is safer to increase. Future work may include adding more parameters to this function, like for example, the current pressure level of the set or the amount that the pressure will be increased/decreased. Reviewers: qcolombet, escha, arsenm, atrick, MatzeB Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14806 llvm-svn: 255795
* MachineScheduler: Print initial pressure in debug dumpMatthias Braun2015-11-131-0/+7
| | | | llvm-svn: 253097
* MachineScheduler: Improve debug output for "only one node in readyset"Matthias Braun2015-11-131-2/+2
| | | | | | | When there is only 1 node left in the ready queue and it is picked call the reason "ONLY1" instead of "NOCAND". llvm-svn: 253096
* MachineScheduler: Add regpressure information to debug dumpMatthias Braun2015-11-061-6/+30
| | | | llvm-svn: 252340
* ScheduleDAGInstrs: Remove IsPostRA flag; NFCMatthias Braun2015-11-031-16/+14
| | | | | | | | | | | | | | | | | ScheduleDAGInstrs doesn't behave differently before or after register allocation. It was only used in a method of MachineSchedulerBase which behaved differently in MachineScheduler/PostMachineScheduler. Change this to let MachineScheduler/PostMachineScheduler just pass in a parameter to that function. The order of the LiveIntervals* and bool RemoveKillFlags paramters have been switched to make out-of-tree code fail instead of unintentionally passing a value intended for the IsPostRA flag to the (previously following and default initialized) RemoveKillFlags. Differential Revision: http://reviews.llvm.org/D14245 llvm-svn: 251883
* Revert "ScheduleDAGInstrs: Remove IsPostRA flag"Matthias Braun2015-10-291-14/+16
| | | | | | | | It broke 3 arm testcases. This reverts commit r251608. llvm-svn: 251615
* MachineScheduler: Fix typo in debug messageMatthias Braun2015-10-291-1/+1
| | | | | | Maybe I just missed the humor there ;-) llvm-svn: 251609
* ScheduleDAGInstrs: Remove IsPostRA flagMatthias Braun2015-10-291-16/+14
| | | | | | | | This was a layering violation in ScheduleDAGInstrs (and MachineSchedulerBase) they both shouldn't know directly whether they are used by the PostMachineScheduler or the MachineScheduler. llvm-svn: 251608
* MachineScheduler: Use ranged for and slightly simplify the codeMatthias Braun2015-10-291-11/+12
| | | | llvm-svn: 251607
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