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* Adds cyclic critical path computation and heuristics, temporarily disabled.Andrew Trick2013-08-231-21/+68
| | | | | | | | | | | Estimate the cyclic critical path within a single block loop. If the acyclic critical path is longer, then the loop will exhaust OOO resources after some number of iterations. If lag between the acyclic critical path and cyclic critical path is longer the the time it takes to issue those loop iterations, then aggressively schedule for latency. llvm-svn: 189120
* mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr ↵Andrew Trick2013-08-231-5/+7
| | | | | | | | | count. This fixes a pathological compile time problem with very large blocks and lots of scheduling boundaries. llvm-svn: 189116
* Confusing comment typo.Andrew Trick2013-08-071-1/+1
| | | | llvm-svn: 187895
* MI Sched: Track live-thru registers.Andrew Trick2013-07-301-2/+10
| | | | | | | | | | | When registers must be live throughout the scheduling region, increase the limit for the register class. Once we exceed the original limit, they will be spilled, and there's no point further reducing pressure. This isn't a perfect heuristics but avoids a situation where the scheduler could become trapped by trying to achieve the impossible. llvm-svn: 187436
* MI Sched fix: assert "Disconnected LRG within the scheduling region."Andrew Trick2013-07-301-0/+6
| | | | llvm-svn: 187435
* MI Sched: Register pressure heuristics.Andrew Trick2013-07-251-8/+32
| | | | | | Consider which set is being increased or decreased before comparing. llvm-svn: 187110
* Dump LIS before regalloc. MI sched changes them.Andrew Trick2013-07-251-2/+2
| | | | llvm-svn: 187107
* Fix uninitialized memory read found by MemorySanitizer: always set output ↵Alexey Samsonov2013-07-191-1/+1
| | | | | | parameter of ConvergingScheduler::SchedBoundary::getOtherResourceCount llvm-svn: 186658
* MI Sched: Update the way resources are tracked so the current heuristics ↵Andrew Trick2013-07-191-7/+5
| | | | | | make more sense. llvm-svn: 186632
* MI-Sched: cleanup DEBUG output.Andrew Trick2013-06-211-5/+6
| | | | llvm-svn: 184565
* MI-Sched: Adjust regpressure limits for reserved regs.Andrew Trick2013-06-211-2/+3
| | | | llvm-svn: 184564
* Give RegMax higher priority.Andrew Trick2013-06-171-9/+9
| | | | llvm-svn: 184133
* Remove compareRPDelta.Andrew Trick2013-06-171-37/+0
| | | | | | A complex, expensive heuristic with little value in the current design. llvm-svn: 184132
* MI-Sched: Remove another heuristic that is sensitive to queue order.Andrew Trick2013-06-171-6/+0
| | | | llvm-svn: 184130
* MI-Sched: Track multiple candidates with the same priority level.Andrew Trick2013-06-171-32/+25
| | | | | | | | This eliminates the MultiPressure scheduling "reason". It was sensitive to queue order. We don't like being sensitive to queue order. llvm-svn: 184129
* Missing NDEBUGs.Andrew Trick2013-06-151-0/+6
| | | | llvm-svn: 184039
* MI-Sched: heuristics using the new latency and machine model.Andrew Trick2013-06-151-234/+330
| | | | llvm-svn: 184038
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-13/+16
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
* MI-Sched: Rename IssueCount to CurrMOps.Andrew Trick2013-06-151-8/+8
| | | | | | | "Counts" refer to scaled resource counts within a region. CurrMOps is simply the number of micro-ops to be issue in the current cycle. llvm-svn: 184031
* MI-Sched: Remove the temporary EnableCopyConstrain flag.Andrew Trick2013-06-151-7/+1
| | | | llvm-svn: 184030
* MI-Sched: added tracking of dependent latency for better heuristics.Andrew Trick2013-06-151-13/+26
| | | | | | | | | | | | | | Heuristics compare the critical path in the scheduled code, called ExpectedLatency, with the latency of instructions remaining to be scheduled. There are two ways to look at remaining latency: (1) Dependent latency includes the latency between unscheduled and scheduled instructions. (2) Independent latency is simply the height (bottom-up) or depth (top-down) of instructions currently in the ready Q. llvm-svn: 184029
* MI-Sched: DEBUG: print critical resource.Andrew Trick2013-06-151-0/+4
| | | | llvm-svn: 184028
* Move #include from .h to .cpp file.Jakub Staszak2013-06-141-0/+1
| | | | llvm-svn: 183960
* MI Sched: revert a minor heuristic that snuck in with -misched-vcopy.Andrew Trick2013-04-301-0/+6
| | | | | | I'll fix the heuristic in a general way in a follow-up commit. llvm-svn: 180815
* Fix for r180193 - MI Sched: eliminate local vreg.Andrew Trick2013-04-241-2/+6
| | | | | | | | | Fixes PR15838. Need to check for blocks with nothing but dbg.value. I'm not sure how to force this situation with a unit test. I tried to reduce the test case in PR15838 (1k lines of metadata) but gave up. llvm-svn: 180227
* MI Sched: eliminate local vreg copies.Andrew Trick2013-04-241-7/+194
| | | | | | | | | | | | | | | | For now, we just reschedule instructions that use the copied vregs and let regalloc elliminate it. I would really like to eliminate the copies on-the-fly during scheduling, but we need a complete implementation of repairIntervalsInRange() first. The general strategy is for the register coalescer to eliminate as many global copies as possible and shrink live ranges to be extended-basic-block local. The coalescer should not have to worry about resolving local copies (e.g. it shouldn't attemp to reorder instructions). The scheduler is a much better place to deal with local interference. The coalescer side of this equation needs work. llvm-svn: 180193
* MI Sched: regpressure tracing.Andrew Trick2013-04-241-0/+8
| | | | llvm-svn: 180191
* MI-Sched: DEBUG formatting.Andrew Trick2013-04-131-14/+22
| | | | llvm-svn: 179452
* MI-Sched: schedule physreg copies.Andrew Trick2013-04-131-1/+72
| | | | | | | | | | | The register allocator expects minimal physreg live ranges. Schedule physreg copies accordingly. This is slightly tricky when they occur in the middle of the scheduling region. For now, this is handled by rescheduling the copy when its associated instruction is scheduled. Eventually we may instead bundle them, but only if we can preserve the bundles as parallel copies during regalloc. llvm-svn: 179449
* RegisterPressure heuristics currently require signed comparisons.Andrew Trick2013-04-051-2/+2
| | | | llvm-svn: 178823
* Disable DFSResult for ConvergingScheduler.Andrew Trick2013-04-051-2/+0
| | | | | | | | For now, just save the compile time since the ConvergingScheduler heuristics don't use this analysis. We'll probably enable it later after compile-time investigation. llvm-svn: 178822
* MachineScheduler: format DEBUG output.Andrew Trick2013-04-051-22/+17
| | | | | | | I'm getting more serious about tuning and enabling on x86/ARM. Start by making the trace readable. llvm-svn: 178821
* Fix missing std::. Not sure how this compiles for anyone else.Matt Arsenault2013-03-211-1/+1
| | | | llvm-svn: 177620
* Cleanup #includes.Jakub Staszak2013-03-101-0/+2
| | | | llvm-svn: 176787
* Add -verify-misched option.Andrew Trick2013-03-081-0/+9
| | | | | | | | | | This verifies live intervals both before and after scheduling. It's useful for anyone hacking on live interval update. Note that we don't yet pass verification all the time. We don't yet handle updating nonallocatable live intervals perfectly. llvm-svn: 176685
* Use const reference instead of vector object when passing an argument toJakub Staszak2013-02-161-1/+1
| | | | | | updateScheduledPressure method. llvm-svn: 175362
* MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick2013-02-131-1/+6
| | | | llvm-svn: 175067
* MIsched: cleanup code. Use isBoundaryNode().Andrew Trick2013-01-291-2/+4
| | | | llvm-svn: 173775
* Use const reference instead of vector copying.Jakub Staszak2013-01-251-1/+2
| | | | llvm-svn: 173497
* MIsched: Print block name. No functionality.Andrew Trick2013-01-251-1/+2
| | | | llvm-svn: 173433
* MachineScheduler support for viewGraph.Andrew Trick2013-01-251-1/+88
| | | | llvm-svn: 173432
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-251-29/+33
| | | | | | | Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. llvm-svn: 173425
* MISched: Add SchedDFSResult to ScheduleDAGMI to formalize theAndrew Trick2013-01-251-25/+55
| | | | | | interface and allow other strategies to select it. llvm-svn: 173413
* MachineScheduler: enable biasCriticalPath for all DAGs.Andrew Trick2013-01-241-0/+4
| | | | llvm-svn: 173318
* Follow-up typo correction from building the wrong branch.Andrew Trick2013-01-111-2/+2
| | | | llvm-svn: 172224
* Fix typo from r170452. Affects -enable-misched heuristics.Andrew Trick2013-01-111-2/+2
| | | | llvm-svn: 172223
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-091-10/+2
| | | | | | | | | | This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. llvm-svn: 171946
* MISched: Cleanup, redundant statement.Andrew Trick2012-12-181-1/+0
| | | | llvm-svn: 170453
* MISched: Heuristics, compare latency more precisely. It matters more for ↵Andrew Trick2012-12-181-43/+38
| | | | | | some targets. llvm-svn: 170452
* MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to ↵Andrew Trick2012-12-181-3/+0
| | | | | | compute it. llvm-svn: 170451
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