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* TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where ↵Matthias Braun2015-09-251-2/+1
| | | | | | apropriate; NFC llvm-svn: 248623
* MachineRegisterInfo: Introduce isPhysRegUsed()Matthias Braun2015-08-181-0/+12
| | | | | | | | | | | | | | | | This method checks whether a physical regiser or any of its aliases are used in the function. Using this function in SIRegisterInfo::findUnusedReg() should also fix this reported failure: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20150803/292143.html http://reviews.llvm.org/rL242173#inline-533 The report doesn't come with a testcase and I don't know enough about AMDGPU to create one myself. llvm-svn: 245329
* Reset the virtual registers in liveins when clearing the virtual registers.Alex Lorenz2015-07-271-0/+2
| | | | | | | | | This commit zeroes out the virtual register references in the machine function's liveins in the class 'MachineRegisterInfo' when the virtual register definitions are cleared. Reviewers: Matthias Braun llvm-svn: 243290
* MachineRegisterInfo: Remove UsedPhysReg infrastructureMatthias Braun2015-07-141-1/+0
| | | | | | | | | | | | | We have a detailed def/use lists for every physical register in MachineRegisterInfo anyway, so there is little use in maintaining an additional bitset of which ones are used. Removing it frees us from extra book keeping. This simplifies VirtRegMap. Differential Revision: http://reviews.llvm.org/D10911 llvm-svn: 242173
* PrologEpilogInserter: Rewrite API to determine callee save regsiters.Matthias Braun2015-07-141-0/+47
| | | | | | | | | | | | | | | | This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan(): - Rename the function to determineCalleeSaves() - Pass a bitset of callee saved registers by reference, thus avoiding the function-global PhysRegUsed bitset in MachineRegisterInfo. - Without PhysRegUsed the implementation is fine tuned to not save physcial registers which are only read but never modified. Related to rdar://21539507 Differential Revision: http://reviews.llvm.org/D10909 llvm-svn: 242165
* Have TargetRegisterInfo::getLargestLegalSuperClass take aEric Christopher2015-03-101-1/+1
| | | | | | | MachineFunction argument so that it can look up the subtarget rather than using a cached one in some Targets. llvm-svn: 231888
* MachineRegisterInfo can access TII off of the MachineFunction'sEric Christopher2015-01-271-2/+2
| | | | | | | subtarget and so doesn't need the TargetMachine or to access via getSubtargetImpl. Update all callers. llvm-svn: 227160
* Silence more static analyzer warnings.Michael Ilseman2014-12-151-0/+1
| | | | | | | | Add in definedness checks for shift operators, null checks when pointers are assumed by the code to be non-null, and explicit unreachables. llvm-svn: 224255
* Add a flag to enable/disable subregister liveness.Matthias Braun2014-12-101-1/+2
| | | | llvm-svn: 223884
* LiveInterval: Add support to track liveness of subregisters.Matthias Braun2014-12-101-0/+8
| | | | | | This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
* CodeGen: switch raw array to std::vectorDylan Noblesmith2014-08-251-8/+1
| | | | llvm-svn: 216355
* Have MachineRegisterInfo take and store the MachineFunction itEric Christopher2014-08-121-2/+2
| | | | | | | | was created for rather than the TargetMachine since we only needed the TM for the subtarget and we can get that from the MF. llvm-svn: 215432
* Changed the liveness tracking in the RegisterScavengerPedro Artigas2014-08-041-2/+9
| | | | | | | | to use register units instead of registers. reviewed by Jakob Stoklund Olesen. llvm-svn: 214798
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-1/+2
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-9/+9
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* Switch a number of loops in lib/CodeGen over to range-based for-loops, now thatOwen Anderson2014-03-171-10/+10
| | | | | | the MachineRegisterInfo iterators are compatible with it. llvm-svn: 204075
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-14/+15
| | | | | | | | | | operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. llvm-svn: 203865
* Fix for http://llvm.org/bugs/show_bug.cgi?id=18590Ekaterina Romanova2014-03-131-0/+15
| | | | | | | This patch fixes the bug in peephole optimization that folds a load which defines one vreg into the one and only use of that vreg. With debug info, a DBG_VALUE that referenced the vreg considered to be a use, preventing the optimization. The fix is to ignore DBG_VALUE's during the optimization, and undef a DBG_VALUE that references a vreg that gets removed. Patch by Trevor Smigiel! llvm-svn: 203829
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-2/+2
| | | | | | Remove the old functions. llvm-svn: 202636
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-1/+1
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* [RegAlloc] Make tryInstructionSplit less aggressive.Quentin Colombet2014-01-021-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The greedy register allocator tries to split a live-range around each instruction where it is used or defined to relax the constraints on the entire live-range (this is a last chance split before falling back to spill). The goal is to have a big live-range that is unconstrained (i.e., that can use the largest legal register class) and several small local live-range that carry the constraints implied by each instruction. E.g., Let csti be the constraints on operation i. V1= op1 V1(cst1) op2 V1(cst2) V1 live-range is constrained on the intersection of cst1 and cst2. tryInstructionSplit relaxes those constraints by aggressively splitting each def/use point: V1= V2 = V1 V3 = V2 op1 V3(cst1) V4 = V2 op2 V4(cst2) Because of how the coalescer infrastructure works, each new variable (V3, V4) that is alive at the same time as V1 (or its copy, here V2) interfere with V1. Thus, we end up with an uncoalescable copy for each split point. To make tryInstructionSplit less aggressive, we check if the split point actually relaxes the constraints on the whole live-range. If it does not, we do not insert it. Indeed, it will not help the global allocation problem: - V1 will have the same constraints. - V1 will have the same interference + possibly the newly added split variable VS. - VS will produce an uncoalesceable copy if alive at the same time as V1. <rdar://problem/15570057> llvm-svn: 198369
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-0/+3
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-3/+0
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-0/+3
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Notify LiveRangeEdit of new virtual registers.Mark Lacey2013-08-141-1/+3
| | | | | | | | | Add a delegate class to MachineRegisterInfo with a single virtual function, MRI_NoteNewVirtualRegister(). Update LiveRangeEdit to inherit from this delegate class and override the definition of the callback with an implementation that tracks the newly created virtual registers. llvm-svn: 188435
* Directly access objects which may change during compilation.Bill Wendling2013-06-171-20/+31
| | | | llvm-svn: 184121
* Add an MRI::verifyUseLists() function.Jakob Stoklund Olesen2013-04-191-3/+51
| | | | | | | This checks the sanity of the register use lists in the MI intermediate representation. llvm-svn: 179895
* Check register classes also when changing them.Jakob Stoklund Olesen2013-03-131-0/+1
| | | | | | We have the same assertion in createVirtualRegister. llvm-svn: 176959
* Remove liveout lists from MachineRegisterInfo.Jakob Stoklund Olesen2013-02-051-7/+0
| | | | | | | | All targets are now adding return value registers as implicit uses on return instructions, and there is no longer a need for the live out lists. llvm-svn: 174417
* Don't call destructors on MachineInstr and MachineOperand.Jakob Stoklund Olesen2013-01-051-6/+0
| | | | | | | | | | | | | | | | | | | | The series of patches leading up to this one makes llc -O0 run 8% faster. When deallocating a MachineFunction, there is no need to visit all MachineInstr and MachineOperand objects to deallocate them. All their memory come from a BumpPtrAllocator that is about to be purged, and they have empty destructors anyway. This only applies when deallocating the MachineFunction. DeleteMachineInstr() should still be used to recycle MI memory during the codegen passes. Remove the LeakDetector support for MachineInstr. I've never seen it used before, and now it definitely doesn't work. With this patch, leaked MachineInstrs would be much less of a problem since all of their memory will be reclaimed by ~MachineFunction(). llvm-svn: 171599
* Add MachineRegisterInfo::moveOperands().Jakob Stoklund Olesen2013-01-051-0/+49
| | | | | | | | | | | | | This function works like memmove() for MachineOperands, except it also updates any use-def chains containing the moved operands. The use-def chains are updated without affecting the order of operands in the list. That isn't possible when using the removeRegOperandFromUseList() and addRegOperandToUseList() functions. Callers to follow soon. llvm-svn: 171597
* Revert r168630, r168631, and r168633 as these are causing nightly test failures.Chad Rosier2012-11-281-2/+0
| | | | llvm-svn: 168751
* Add an assertion to ensure freezeReservedRegs() is only ever called once.Chad Rosier2012-11-261-0/+2
| | | | llvm-svn: 168633
* Switch MRI::UsedPhysRegs to a register unit bit vector.Jakob Stoklund Olesen2012-10-171-2/+2
| | | | | | | This is a more compact, less redundant representation, and it avoids scanning long lists of aliases for ARM D-registers, for example. llvm-svn: 166124
* Freeze the reserved registers as soon as isel is complete.Jakob Stoklund Olesen2012-10-151-9/+5
| | | | | | | | | | | | | Also provide an MRI::getReservedRegs() function to access the frozen register set, and isReserved() and isAllocatable() methods to test individual registers. The various implementations of TRI::getReservedRegs() are quite complicated, and many passes need to look at the reserved register set. This patch makes it possible for these passes to use the cached copy in MRI, avoiding a lot of malloc traffic and repeated calculations. llvm-svn: 165982
* Reapply r161633-161634 "Partition use lists so defs always come before uses.""Jakob Stoklund Olesen2012-08-101-45/+47
| | | | | | | No changes to these patches, MRI needed to be notified when changing uses into defs and vice versa. llvm-svn: 161644
* Revert r161633-161634 "Partition use lists so defs always come before uses."Jakob Stoklund Olesen2012-08-091-47/+45
| | | | | | These commits broke a number of buildbots. llvm-svn: 161640
* Partition use lists so defs always come before uses.Jakob Stoklund Olesen2012-08-091-3/+11
| | | | | | | | | | | | | | | | This makes it possible to speed up def_iterator by stopping at the first use. This makes def_empty() and getUniqueVRegDef() much faster when there are many uses. In a +Asserts build, LiveVariables is 100x faster in one case because getVRegDef() has an assertion that would scan to the end of a def_iterator chain. Spill weight calculation is significantly faster (300x in one case) because isTriviallyReMaterializable() calls MRI->isConstantPhysReg(%RIP) which calls def_empty(%RIP). llvm-svn: 161634
* Don't use pointer-pointers for the register use lists.Jakob Stoklund Olesen2012-08-091-45/+39
| | | | | | | | | | | Use a more conventional doubly linked list where the Prev pointers form a cycle. This means it is no longer necessary to adjust the Prev pointers when reallocating the VRegInfo array. The test changes are required because the register allocation hint is using the use-list order to break ties. llvm-svn: 161633
* Move use list management into MachineRegisterInfo.Jakob Stoklund Olesen2012-08-091-0/+37
| | | | | | | | | | | | | | Register MachineOperands are kept in linked lists accessible via MRI's reg_iterator interfaces. The linked list management was handled partly by MachineOperand methods, partly by MRI methods. Move all of the list management into MRI, delete MO::AddRegOperandToRegInfo() and MO::RemoveRegOperandFromRegInfo(). Be more explicit about handling the cases where an MRI pointer isn't available. llvm-svn: 161632
* Inline MachineRegisterInfo::hasOneUseAndrew Trick2012-07-301-7/+0
| | | | llvm-svn: 161007
* Added assertion in getVRegDef of MachineRegisterInfo to make sure the virtualManman Ren2012-07-021-0/+2
| | | | | | | register does not have multiple definitions. Modified TwoAddressInstructionPass to use getUniqueVRegDef instead of getVRegDef. llvm-svn: 159545
* Add getUniqueVRegDef to MachineRegisterInfo.Manman Ren2012-06-291-0/+11
| | | | | | This comes in handy during peephole optimization. llvm-svn: 159453
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-4/+4
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Add an MRI::tracksLiveness() flag.Jakob Stoklund Olesen2012-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | Late optimization passes like branch folding and tail duplication can transform the machine code in a way that makes it expensive to keep the register liveness information up to date. There is a fuzzy line between register allocation and late scheduling where the liveness information degrades. The MRI::tracksLiveness() flag makes the line clear: While true, liveness information is accurate, and can be used for register scavenging. Once the flag is false, liveness information is not accurate, and can only be used as a hint. Late passes generally don't need the liveness information, but they will sometimes use the register scavenger to help update it. The scavenger enforces strict correctness, and we have to spend a lot of code to update register liveness that may never be used. llvm-svn: 153511
* Microoptimize getVRegDef. def_begin isn't free, don't compute it twice.Benjamin Kramer2012-03-101-3/+2
| | | | llvm-svn: 152492
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-2/+2
| | | | llvm-svn: 152001
* Clear virtual registers after they are no longer referenced.Andrew Trick2012-02-211-3/+11
| | | | | | | | | | | | | Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0. This makes sharing code for pre/postRA passes more robust. Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA(). To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs(). PEI resets virtual regs when it's done scavenging. PTX will either have to provide its own PEI pass or assign physregs. llvm-svn: 151032
* Transfer regmasks to MRI.Jakob Stoklund Olesen2012-02-171-10/+2
| | | | | | | | | MRI keeps track of which physregs have been used. Make sure it gets updated with all the regmask-clobbered registers. Delete the closePhysRegsUsed() function which isn't necessary. llvm-svn: 150830
* Extract method for detecting constant unallocatable physregs.Jakob Stoklund Olesen2012-01-161-0/+18
| | | | | | It is safe to move uses of such registers. llvm-svn: 148259
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