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* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-161-1/+1
| | | | llvm-svn: 144747
* Disable LICM speculation in high register pressure situation again now that ↵Evan Cheng2011-10-261-1/+1
| | | | | | Devang has fixed other issues. llvm-svn: 143003
* As Evan suggested, loads from constant pool are safe to speculate.Devang Patel2011-10-201-5/+5
| | | | llvm-svn: 142593
* Add a comment.Devang Patel2011-10-201-1/+3
| | | | llvm-svn: 142592
* Constraint register class with constrainRegClass() to CSE a virtual into ↵Evan Cheng2011-10-171-3/+26
| | | | | | another. rdar://10293289 llvm-svn: 142234
* It is safe to speculate load from GOT. This fixes performance regression ↵Devang Patel2011-10-171-1/+17
| | | | | | | | caused by r141689. Radar 10281206. llvm-svn: 142202
* Tabs to spaces.Nick Lewycky2011-10-131-2/+2
| | | | llvm-svn: 141844
* Disable machine LICM speculation check (for profitability) until I have time ↵Evan Cheng2011-10-121-6/+15
| | | | | | to investigate the regressions. llvm-svn: 141813
* Expand the check for a landing pad so that it looks at the basic block'sBill Wendling2011-10-121-5/+11
| | | | | | | containing loop's header to see if that's a landing pad. If it is, then we don't want to hoist instructions out of the loop and above the header. llvm-svn: 141767
* Fix r141744.Evan Cheng2011-10-121-1/+19
| | | | | | | | | 1. The speculation check may not have been performed if the BB hasn't had a load LICM candidate. 2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the instruction even if it's in high register pressure situation. llvm-svn: 141747
* Refine r141689 with a tri-state variable.Evan Cheng2011-10-111-19/+23
| | | | | | Also teach MachineLICM to avoid "speculation" when register pressure is high. llvm-svn: 141744
* N.B. This is with the new EH scheme:Bill Wendling2011-10-111-0/+5
| | | | | | | | | | | | | | | The blocks with invokes have branches to the dispatch block, because that more correctly models the behavior of the CFG. The dispatch of course has edges to the landing pads. Those landing pads could contain invokes, which then have branches back to the dispatch. This creates a loop. The machine LICM pass looks at this loop and thinks it can hoist elements out of it. But because the dispatch is an alternate entry point into the program, the hoisted instructions won't be executed. I wasn't able to get a testcase which was small and could reproduce all of the time. The function_try_block.cpp in llvm-test was where this showed up. llvm-svn: 141726
* Add dominance check for the instruction being hoisted.Devang Patel2011-10-111-1/+46
| | | | | | | For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. llvm-svn: 141689
* Revert r141569 and r141576.Devang Patel2011-10-101-29/+0
| | | | llvm-svn: 141594
* If loop header is also loop exiting block then it may not be safe to hoist ↵Devang Patel2011-10-101-5/+4
| | | | | | instructions. llvm-svn: 141576
* Add dominance check for the instruction being hoisted.Devang Patel2011-10-101-0/+30
| | | | | | | For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. llvm-svn: 141569
* Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. ↵Evan Cheng2011-09-011-27/+40
| | | | | | Sorry, I can't come up with a small test case. rdar://10043690 llvm-svn: 138934
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-291-1/+1
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-3/+3
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-1/+1
| | | | llvm-svn: 133944
* Look pass copies when determining whether hoisting would end up inserting ↵Evan Cheng2011-04-111-8/+17
| | | | | | more copies. rdar://9266679 llvm-svn: 129297
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-071-1/+1
| | | | llvm-svn: 127175
* Sorry, several patches in one.Evan Cheng2011-01-201-40/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-4/+4
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Add a FIXME comment.Dan Gohman2010-11-111-0/+2
| | | | llvm-svn: 118803
* MachineLICM should not claim to be preserving the CFG when it can split criticalJakob Stoklund Olesen2010-11-011-1/+0
| | | | | | edges on demand. llvm-svn: 117982
* Use instruction itinerary to determine what instructions are 'cheap'.Evan Cheng2010-10-261-4/+36
| | | | llvm-svn: 117348
* More accurate estimate / tracking of register pressure.Evan Cheng2010-10-201-64/+121
| | | | | | | | | | - Initial register pressure in the loop should be all the live defs into the loop. Not just those from loop preheader which is often empty. - When an instruction is hoisted, update register pressure from loop preheader to the original BB. - Treat only use of a virtual register as kill since the code is still SSA. llvm-svn: 116956
* Make CodeGen TBAA-aware.Dan Gohman2010-10-201-1/+3
| | | | llvm-svn: 116890
* Re-enable register pressure aware machine licm with fixes. Hoist() may haveEvan Cheng2010-10-191-77/+58
| | | | | | | erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. llvm-svn: 116845
* Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson2010-10-191-2/+6
| | | | | | | | | | | | | | | | | exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. llvm-svn: 116820
* Revert r116781 "- Add a hook for target to determine whether an instruction defDaniel Dunbar2010-10-191-36/+52
| | | | | | is", which breaks some nightly tests. llvm-svn: 116816
* Fix for machine licm assert: RCCost <= RegPressure[RCId]Andrew Trick2010-10-191-2/+2
| | | | | | | in MultiSource/Benchmarks/VersaBench/beamformer/beamformer. SmallSet.insert returns true if the element is inserted. llvm-svn: 116790
* - Add a hook for target to determine whether an instruction def isEvan Cheng2010-10-191-52/+36
| | | | | | | | | | | "long latency" enough to hoist even if it may increase spilling. Reloading a value from spill slot is often cheaper than performing an expensive computation in the loop. For X86, that means machine LICM will hoist SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON instructions. - Enable register pressure aware machine LICM by default. llvm-svn: 116781
* More machine LICM work. It now tracks register pressure for path from ↵Evan Cheng2010-10-161-69/+155
| | | | | | preheader to current BB and use the information determine whether hoisting is worthwhile. llvm-svn: 116654
* Register pressure and instruction latency aware machine LICM. Work in progress.Evan Cheng2010-10-141-26/+242
| | | | llvm-svn: 116465
* Begin adding static dependence information to passes, which will allow us toOwen Anderson2010-10-121-1/+6
| | | | | | | | | perform initialization without static constructors AND without explicit initialization by the client. For the moment, passes are required to initialize both their (potential) dependencies and any passes they preserve. I hope to be able to relax the latter requirement in the future. llvm-svn: 116334
* Don't waste time unfolding simple loads. The unfolded copy won't be hoisted.Evan Cheng2010-10-081-0/+4
| | | | llvm-svn: 116081
* Now with fewer extraneous semicolons!Owen Anderson2010-10-071-1/+1
| | | | llvm-svn: 115996
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-2/+2
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Comment typo.Dale Johannesen2010-07-291-1/+1
| | | | llvm-svn: 109765
* Fix batch of converting RegisterPass<> to INTIALIZE_PASS().Owen Anderson2010-07-211-2/+2
| | | | llvm-svn: 109045
* Fix test for switch statements and increaseDale Johannesen2010-07-201-2/+3
| | | | | | threshold a bit per experimentation. llvm-svn: 108935
* Don't hoist things out of a large switch inside aDale Johannesen2010-07-201-2/+6
| | | | | | | | | | loop, for the reasons in the comments. This is a major win on 253.perlbmk on ARM Darwin. I expect it to be a good heuristic in general, but it's possible some things will regress; I'll be watching. 7940152. llvm-svn: 108792
* Teach ProcessImplicitDefs to transform more COPY instructions into ↵Evan Cheng2010-07-141-6/+3
| | | | | | IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620. llvm-svn: 108304
* change machinelicm to use MachineInstr::isSafeToMove. NoChris Lattner2010-07-121-18/+8
| | | | | | | | intended functionality change. The avoidance of hoistiing implicitdef seems wrong though. llvm-svn: 108109
* Fix MachineLICM to actually visit inner loops.Dan Gohman2010-07-091-3/+11
| | | | llvm-svn: 108001
* Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks outDan Gohman2010-06-221-23/+50
| | | | | | | into a utility routine, teach it how to update MachineLoopInfo, and make use of it in MachineLICM to split critical edges on demand. llvm-svn: 106555
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