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* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-0/+1
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-9/+8
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* More cleanups for MachineOperand:Chris Lattner2007-12-301-110/+114
| | | | | | | | | | - Eliminate the static "print" method for operands, moving it into MachineOperand::print. - Change various set* methods for register flags to take a bool for the value to set it to. Remove unset* methods. - Group methods more logically by operand flavor in MachineOperand.h llvm-svn: 45461
* MachineOperand:Chris Lattner2007-12-301-57/+38
| | | | | | | | | | | | | | | | | - Add getParent() accessors. - Move SubReg out of the AuxInfo union, to make way for future changes. - Remove the getImmedValue/setImmedValue methods. - in some MachineOperand::Create* methods, stop initializing fields that are dead. MachineInstr: - Delete one copy of the MachineInstr printing code, now there is only one dump format and one copy of the code. - Make MachineOperand use the parent field to get info about preg register names if no target info is otherwise available. - Move def/use/kill/dead flag printing to the machineoperand printer, so they are always printed for an operand. llvm-svn: 45460
* simpilfy some register printing code.Chris Lattner2007-12-301-16/+6
| | | | llvm-svn: 45458
* eliminate a copy of the machineoperand printing stuff. Keep the copy thatChris Lattner2007-12-301-34/+4
| | | | | | knows how to print offsets. llvm-svn: 45457
* Simplify and clean up some machine operand/instr printing/dumping stuff.Chris Lattner2007-12-301-9/+9
| | | | llvm-svn: 45456
* two register machineoperands are not identical unless their subregs match.Chris Lattner2007-12-301-1/+2
| | | | llvm-svn: 45455
* MachineOperand::getImmedValue -> MachineOperand::getImmChris Lattner2007-12-301-2/+2
| | | | llvm-svn: 45454
* make machine operands fatter: give each one an up-pointer to the Chris Lattner2007-12-301-1/+7
| | | | | | machineinstr that owns it. llvm-svn: 45449
* Start using the simplified methods for adding operands.Chris Lattner2007-12-301-8/+3
| | | | llvm-svn: 45432
* simplify some code by factoring operand construction better.Chris Lattner2007-12-301-22/+4
| | | | llvm-svn: 45428
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Clean up sub-register implementation by moving subReg information back toEvan Cheng2007-11-141-0/+2
| | | | | | | | | | | MachineOperand auxInfo. Previous clunky implementation uses an external map to track sub-register uses. That works because register allocator uses a new virtual register for each spilled use. With interval splitting (coming soon), we may have multiple uses of the same register some of which are of using different sub-registers from others. It's too fragile to constantly update the information. llvm-svn: 44104
* Optionally create a MachineInstr without default implicit operands.Evan Cheng2007-10-131-4/+5
| | | | llvm-svn: 42945
* EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG likeEvan Cheng2007-10-121-0/+18
| | | | | | | | | (almost) a register copy. However, it always coalesced to the register of the RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub- register uses which adds subtle complications to load folding, spiller rewrite, etc. llvm-svn: 42899
* Remove isReg, isImm, and isMBB, and change all their users to use Dan Gohman2007-09-141-7/+7
| | | | | | | isRegister, isImmediate, and isMachineBasicBlock, which are equivalent, and more popular. llvm-svn: 41958
* Remove spurious consts. This fixes warnings with compilers thatDan Gohman2007-09-141-1/+1
| | | | | | are strict about such things. llvm-svn: 41956
* Remove subreg index from MachineInstr's and also keep vregs as unsigned when ↵Christopher Lamb2007-07-261-2/+0
| | | | | | adding operands. llvm-svn: 40514
* MachineInstr::isPredicable() is no longer needed.Evan Cheng2007-06-151-4/+0
| | | | llvm-svn: 37599
* Add missing const qualifiers.Evan Cheng2007-05-291-7/+8
| | | | llvm-svn: 37341
* Rename M_PREDICATED to M_PREDICABLE; Moved isPredicable() to MachineInstr.Evan Cheng2007-05-161-2/+6
| | | | llvm-svn: 37121
* Added getNumExplicitOperands and findFirstPredOperand.Evan Cheng2007-05-151-0/+46
| | | | llvm-svn: 37064
* llvm bug #1350, parts 1, 2, and 3.Nate Begeman2007-05-011-2/+2
| | | | llvm-svn: 36618
* Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.Evan Cheng2007-04-261-2/+2
| | | | llvm-svn: 36483
* Change findRegisterUseOperand() to return operand index instead.Evan Cheng2007-03-261-4/+4
| | | | llvm-svn: 35363
* Use findRegisterUseOperand to find a kill of particular register.Evan Cheng2007-02-231-3/+5
| | | | llvm-svn: 34512
* Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.Evan Cheng2007-02-191-0/+11
| | | | llvm-svn: 34428
* For PR1207:Reid Spencer2007-02-191-11/+0
| | | | | | | Revert patches that caused the problem. Evan, please investigate and reapply when you've discovered the problem. llvm-svn: 34399
* Added findRegisterDefOperand().Evan Cheng2007-02-171-0/+11
| | | | llvm-svn: 34380
* Print <dead> def operands.Evan Cheng2007-02-161-0/+2
| | | | llvm-svn: 34343
* The best unbreakage yet, addressing Bill's concerns.Jeff Cohen2006-12-161-41/+28
| | | | llvm-svn: 32622
* An even better unbreakage...Jeff Cohen2006-12-151-0/+12
| | | | llvm-svn: 32617
* Changed llvm_ostream et all to OStream. llvm_cerr, llvm_cout, llvm_null, areBill Wendling2006-12-071-2/+1
| | | | | | now cerr, cout, and NullStream resp. llvm-svn: 32298
* Move copyKillDeadInfo out-of-line. Add findRegisterUseOperand().Evan Cheng2006-12-061-0/+31
| | | | llvm-svn: 32273
* - MachineInstr now keeps a ptr to TargetInstrDescriptor instead of Opcode.Evan Cheng2006-11-301-42/+35
| | | | | | - Remove the ugly TargetInstrDescriptors hack. llvm-svn: 32032
* Use llvm streams instead of <iostream>Bill Wendling2006-11-281-2/+2
| | | | llvm-svn: 31985
* Clean up.Evan Cheng2006-11-281-2/+2
| | | | llvm-svn: 31957
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-20/+14
| | | | | | of opcode and number of operands. llvm-svn: 31947
* setOperand should not zap the operand list or add implicit operands to anChris Lattner2006-11-201-39/+0
| | | | | | | | | instruction. Doing so breaks the FP stackifier, the alpha branch selector the sparc fpmover. This fixes PR1012 and CodeGen/X86/fp-stack-compare.ll llvm-svn: 31876
* Minor updates.Evan Cheng2006-11-151-4/+4
| | | | llvm-svn: 31761
* - Let MachineInstr ctors add implicit def and use operands. Other operandsEvan Cheng2006-11-131-16/+113
| | | | | | | | | will be inserted before these operands. If the opcode changes (by setOpcode), the implicit operands are updated as well. - Added IsKill, IsDead fields to MachineOperand in preparation for changes that move kill / dead info to MachineInstr's. llvm-svn: 31711
* Add methods to add implicit def use operands to a MI.Evan Cheng2006-11-111-0/+12
| | | | llvm-svn: 31675
* Add implicit def / use operands to MachineInstr.Evan Cheng2006-11-101-2/+6
| | | | llvm-svn: 31633
* be more aggressive about matching identical instructions.Chris Lattner2006-10-251-1/+1
| | | | llvm-svn: 31179
* implement MachineOperand::isIdenticalToChris Lattner2006-10-201-0/+29
| | | | llvm-svn: 31088
* Only call isUse/isDef on register operandsChris Lattner2006-09-051-11/+5
| | | | llvm-svn: 30118
* Instructions with variable operands (variable_ops) can have a number requiredEvan Cheng2006-06-151-1/+2
| | | | | | | | | | | | | operands. e.g. def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops), "call {*}$dst", [(X86call GR32:$dst)]>; TableGen should emit operand informations for the "required" operands. Added a target instruction info flag M_VARIABLE_OPS to indicate the target instruction may have more operands in addition to the minimum required operands. llvm-svn: 28791
* Remove a bogus cast.Evan Cheng2006-05-261-1/+1
| | | | llvm-svn: 28492
* Final pass of minor cleanups for MachineInstrChris Lattner2006-05-041-4/+0
| | | | llvm-svn: 28110
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