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* Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a ↵Jakob Stoklund Olesen2010-05-211-15/+11
| | | | | | | | register is read." This reverts r104322. I think it was causing miscompilations. llvm-svn: 104323
* Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.Jakob Stoklund Olesen2010-05-211-11/+15
| | | | | | This correctly handles partial redefines and undef uses. llvm-svn: 104322
* If the first definition of a virtual register is a partial redef, add anJakob Stoklund Olesen2010-05-211-5/+15
| | | | | | | <imp-def> operand for the full register. This ensures that the full physical register is marked live after register allocation. llvm-svn: 104320
* Add MachineInstr::readsVirtualRegister() in preparation for proper handling ofJakob Stoklund Olesen2010-05-191-1/+24
| | | | | | | | | | | | | | | | | | partial redefines. We are going to treat a partial redefine of a virtual register as a read-modify-write: %reg1024:6 = OP Unless the register is fully clobbered: %reg1024:6 = OP, %reg1024<imp-def> MachineInstr::readsVirtualRegister() knows the difference. The first case is a read, the second isn't. llvm-svn: 104149
* Teach MachineLICM and MachineSink how to clear kill flags conservativelyDan Gohman2010-05-131-0/+10
| | | | | | when they move instructions. llvm-svn: 103737
* Pretty print DBG_VALUE machine instructions.Evan Cheng2010-04-281-1/+9
| | | | | | | | | Before: DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707 Now: DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707 llvm-svn: 102518
* Use getNumImplicitDefs() and getNumImplicitUses().Bob Wilson2010-04-091-24/+6
| | | | llvm-svn: 100850
* Fix up some comments.Bob Wilson2010-04-091-5/+3
| | | | llvm-svn: 100849
* Coalescer should not delete copy instructions whose defs are partially dead. ↵Evan Cheng2010-04-081-0/+13
| | | | | | | | e.g. %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def> llvm-svn: 100804
* fix a latent bug my inline asm stuff exposed: Chris Lattner2010-04-071-0/+2
| | | | | | MachineOperand::isIdenticalTo wasn't handling metadata operands. llvm-svn: 100636
* stop using DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-5/+3
| | | | llvm-svn: 100215
* Switch the code generator (except the JIT) onto the new DebugLocChris Lattner2010-04-021-5/+4
| | | | | | | | | | | | | | | representation. This eliminates the 'DILocation' MDNodes for file/line/col tuples from -O0 -g codegen. This remove the old DebugLoc class, making it a typedef for DebugLoc, I'll rename NewDebugLoc next. I didn't update the JIT to use the new apis, so it will continue to work, but be as slow as before. Someone should eventually do this or, better yet, rip out the JIT debug info stuff and build the JIT on top of MC. llvm-svn: 100209
* add support for MCSymbols as operands to MachineInstrs.Chris Lattner2010-03-131-25/+34
| | | | llvm-svn: 98433
* Avoid using DIDescriptor.isNull(). Devang Patel2010-03-081-1/+1
| | | | | | This is a first step towards eliminating checks in Descriptor constructors. llvm-svn: 97975
* Revert r97947.Devang Patel2010-03-081-1/+1
| | | | llvm-svn: 97963
* Avoid using DIDescriptor.isNull().Devang Patel2010-03-081-1/+1
| | | | | | This is a first step towards eliminating unncessary constructor checks in light weight DIDescriptor wrappers. llvm-svn: 97947
* Move MachineInstrExpressionTrait::getHashValue() out of line so it can skip ↵Evan Cheng2010-03-031-0/+45
| | | | | | over only virtual register defs. This matches what isEqual() is doing. llvm-svn: 97680
* Fix funky indentation and add comments.Evan Cheng2010-03-031-17/+24
| | | | llvm-svn: 97670
* - Change MachineInstr::isIdenticalTo to take a new option that determines ↵Evan Cheng2010-03-031-0/+23
| | | | | | | | whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). llvm-svn: 97628
* Swap parameters of isSafeToMove and isSafeToReMat for consistency.Evan Cheng2010-03-021-5/+5
| | | | llvm-svn: 97578
* Add non-temporal flags to MachineMemOperand.David Greene2010-02-151-2/+3
| | | | llvm-svn: 96226
* Fix "the the" and similar typos.Dan Gohman2010-02-101-1/+1
| | | | llvm-svn: 95781
* Add isDebug argument to ChangeToRegister; this preventsDale Johannesen2010-02-101-1/+3
| | | | | | the field from being used uninitialized later in some cases. llvm-svn: 95735
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-17/+3
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* Identify predicate and optional-def operands when printing machineJakob Stoklund Olesen2010-01-191-0/+7
| | | | | | instructions. llvm-svn: 93925
* Replace DebugLocTuple with DILocation.Devang Patel2010-01-161-5/+5
| | | | llvm-svn: 93630
* Further progration of metadata operands. TheDale Johannesen2010-01-131-1/+7
| | | | | | | dumper doesn't really do what I want yet, but at least it doesn't crash now. llvm-svn: 93272
* Add <imp-def> and <imp-kill> operands when replacing virtual sub-register ↵Jakob Stoklund Olesen2010-01-061-0/+9
| | | | | | | | | | | | | | defs and kills. An instruction like this: %reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0 Must be replaced with this when substituting physical registers: %S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def> llvm-svn: 92812
* Change errs() to dbgs().David Greene2010-01-041-1/+2
| | | | llvm-svn: 92545
* snip one more #include from Metadata.hChris Lattner2009-12-281-0/+1
| | | | llvm-svn: 92214
* Remove dead store.Bill Wendling2009-12-251-1/+1
| | | | llvm-svn: 92159
* Remove dead store from copy-pasto.Bill Wendling2009-12-251-1/+1
| | | | llvm-svn: 92158
* Add @earlyclobber TableGen constraintJim Grosbach2009-12-161-3/+21
| | | | llvm-svn: 91554
* Follow up to 90488. Turn a check into an assertion.Evan Cheng2009-12-071-2/+2
| | | | llvm-svn: 90815
* Don't print the debug directory; it's often long and uninteresting. OmitDan Gohman2009-12-051-2/+7
| | | | | | | the column number if it is not known. Handle the case of a missing filename better. llvm-svn: 90630
* Watch out for PHI instruction with no source operands.Evan Cheng2009-12-031-0/+2
| | | | llvm-svn: 90488
* Fill out codegen SSA updater. It's not yet tested.Evan Cheng2009-12-031-0/+14
| | | | llvm-svn: 90395
* Devang pointed out that this code should use DIScope instead ofDan Gohman2009-12-011-3/+3
| | | | | | DICompileUnit. This code now prints debug filenames successfully. llvm-svn: 90181
* Print the debug info line and column in MachineInstr::print even when there'sDan Gohman2009-11-231-2/+3
| | | | | | no filename. This situation is apparently fairly common right now. llvm-svn: 89701
* Initialize the new AsmPrinterFlags field to 0, fixing uses ofDan Gohman2009-11-161-6/+8
| | | | | | uninitialized memory. llvm-svn: 88985
* Print "..." instead of all the uninteresting register clobbers on callDan Gohman2009-11-091-14/+54
| | | | | | | | | | | | instructions. This makes CodeGen dumps significantly less noisy. Example before: BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead> Same example after: BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ... llvm-svn: 86583
* Use WriteAsOperand to print GlobalAddress MachineOperands. ThisDan Gohman2009-11-061-1/+2
| | | | | | prints them with the leading '@'. llvm-svn: 86261
* Make -print-machineinstrs more readable.Dan Gohman2009-10-311-19/+28
| | | | | | | | | | | | | | - Be consistent when referring to MachineBasicBlocks: BB#0. - Be consistent when referring to virtual registers: %reg1024. - Be consistent when referring to unknown physical registers: %physreg10. - Be consistent when referring to known physical registers: %RAX - Be consistent when referring to register 0: %reg0 - Be consistent when printing alignments: align=16 - Print jump table contents. - Don't print host addresses, in general. - and various other cleanups. llvm-svn: 85682
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-301-0/+10
| | | | llvm-svn: 85556
* Need a comma after imp-use.Evan Cheng2009-10-211-1/+3
| | | | llvm-svn: 84749
* Print earlyclobber for implicit-defs as well.Evan Cheng2009-10-141-6/+6
| | | | llvm-svn: 84152
* s/DebugLoc.CompileUnit/DebugLoc.Scope/gDevang Patel2009-10-131-5/+6
| | | | | | s/DebugLoc.InlinedLoc/DebugLoc.InlinedAtLoc/g llvm-svn: 84054
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-091-5/+7
| | | | | | | | | | | | | | is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. llvm-svn: 83687
* isTriviallyReMaterializable checks theDan Gohman2009-10-091-2/+1
| | | | | | | TargetInstrDesc::isRematerializable flag, so it isn't necessary to do this check in its callers. llvm-svn: 83671
* Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman2009-10-071-1/+42
| | | | | | | | | implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. llvm-svn: 83475
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