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path: root/llvm/lib/CodeGen/MachineCopyPropagation.cpp
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* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-221-3/+2
| | | | llvm-svn: 182531
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-7/+7
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Convert COPY instructions into KILLs if they have implicit defs.Jakob Stoklund Olesen2012-11-301-3/+17
| | | | | | | | | | | MachineCopyPropagation doesn't understand super-register liveness well enough to be able to remove implicit defs of super-registers. This fixes a problem in ARM/2012-01-26-CopyPropKills.ll that is exposed by an future TwoAddressInstructionPass change. The KILL instructions are removed before the machine code is emitted. llvm-svn: 169060
* Remove unneeded #include.Jakub Staszak2012-11-271-1/+0
| | | | llvm-svn: 168664
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-151-6/+7
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. llvm-svn: 165983
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-5/+5
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Switch some getAliasSet clients to MCRegAliasIterator.Jakob Stoklund Olesen2012-06-011-30/+10
| | | | | | | MCRegAliasIterator can optionally visit the register itself, allowing for simpler code. llvm-svn: 157837
* Use a SmallVector and linear lookup instead of a DenseSet - SourceMap valuesLang Hames2012-03-271-11/+16
| | | | | | | will always be tiny sets, so DenseSet is overkill (SmallSet won't work as we need iteration support). llvm-svn: 153529
* During MachineCopyPropagation a register may be the source operand of multipleLang Hames2012-03-271-17/+26
| | | | | | | | | | copies being considered for removal. Make sure to track all of the copies, rather than just the most recent encountered, by holding a DenseSet instead of an unsigned in SrcMap. No test case - couldn't reduce something with a sane size. llvm-svn: 153487
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-3/+3
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-5/+5
| | | | llvm-svn: 152001
* Fix for PR12090: clear def maps of aliases when visiting a copy. e.g.Evan Cheng2012-02-271-0/+5
| | | | | | | | | %S5<def> = COPY %S0<kill> First clear def map of Q1, etc. No small test case available. llvm-svn: 151574
* Fix machine-cp by having it to check sub-register indicies. e.g.Evan Cheng2012-02-201-2/+26
| | | | | | | | | | | | ecx = mov eax al = mov ch The second copy is not a nop because the sub-indices of ecx,ch is not the same of that of eax/al. Re-enabled machine-cp. PR11940 llvm-svn: 151002
* Erase dead copies that are clobbered by a call.Jakob Stoklund Olesen2012-02-091-5/+17
| | | | | | This does make a difference, at least when using RABasic. llvm-svn: 150118
* Handle register masks in MachineCopyPropagation.Jakob Stoklund Olesen2012-02-081-0/+17
| | | | | | | | For simplicity, treat calls with register masks as basic block boundaries. This means we can't copy propagate callee-saved registers across calls, but I don't think that is a big deal. llvm-svn: 150108
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-081-4/+1
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* whitespaceAndrew Trick2012-02-081-1/+1
| | | | llvm-svn: 150094
* Clear kill flags before propagating a copy.Jakob Stoklund Olesen2012-01-261-1/+6
| | | | | | | | | | The live range of the source register may be extended when a redundant copy is eliminated. Make sure any kill flags between the two copies are cleared. This fixes PR11765. llvm-svn: 149069
* Avoid eraseing copies from a reserved register unless the definition can beEvan Cheng2012-01-081-0/+26
| | | | | | safely proven not to have been clobbered. No small test case possible. llvm-svn: 147751
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-071-0/+240
opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
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