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* [MIR] Teach the printer how to print complex types for generic machine ↵Quentin Colombet2016-03-081-1/+2
| | | | | | | | | | | | | instructions. Before this change, we would get the type definition in the middle of the instruction. E.g., %0(48) = G_ADD %struct_alias = type { i32, i16 } %edi, %edi Now, we have just the expected type name: %0(48) = G_ADD %struct_alias %edi, %edi llvm-svn: 262885
* [MIR] Print the type of generic machine instructions.Quentin Colombet2016-03-081-0/+4
| | | | llvm-svn: 262880
* [MIR] Teach the MIPrinter about size for generic virtual registers.Quentin Colombet2016-03-071-4/+12
| | | | llvm-svn: 262867
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. (This is the second attempt to submit this patch. The first caused two assertion failures and was reverted. See https://llvm.org/bugs/show_bug.cgi?id=25687) The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254377
* Revert r254348: "Replace all weight-based interfaces in MBB with ↵Hans Wennborg2015-12-011-2/+2
| | | | | | | | | | probability-based interfaces, and update all uses of old interfaces." and the follow-up r254356: "Fix a bug in MachineBlockPlacement that may cause assertion failure during BranchProbability construction." Asserts were firing in Chromium builds. See PR25687. llvm-svn: 254366
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254348
* TargetRegisterInfo: Introduce PrintLaneMask.Matthias Braun2015-09-251-2/+1
| | | | | | | This makes it more convenient to print lane masks and lead to more uniform printing. llvm-svn: 248624
* Save LaneMask with livein registersMatthias Braun2015-09-091-2/+5
| | | | | | | | | | | | | | | | | With subregister liveness enabled we can detect the case where only parts of a register are live in, this is expressed as a 32bit lanemask. The current code only keeps registers in the live-in list and therefore enumerated all subregisters affected by the lanemask. This turned out to be too conservative as the subregister may also cover additional parts of the lanemask which are not live. Expressing a given lanemask by enumerating a minimum set of subregisters is computationally expensive so the best solution is to simply change the live-in list to store the lanemasks as well. This will reduce memory usage for targets using subregister liveness and slightly increase it for other targets Differential Revision: http://reviews.llvm.org/D12442 llvm-svn: 247171
* [WinEH] Add some support for code generating catchpadReid Kleckner2015-08-271-1/+1
| | | | | | | We can now run 32-bit programs with empty catch bodies. The next step is to change PEI so that we get funclet prologues and epilogues. llvm-svn: 246235
* MachineBasicBlock: Add liveins() method returning an iterator_rangeMatthias Braun2015-08-241-3/+5
| | | | llvm-svn: 245895
* MIR Serialization: Serialize the pointer IR expression values in the machineAlex Lorenz2015-08-211-6/+7
| | | | | | memory operands. llvm-svn: 245745
* MIR Serialization: Print MCSymbol operands.Alex Lorenz2015-08-211-3/+4
| | | | | | | | This commit allows the MIR printer to print the MCSymbol machine operands. Unfortunately they can't be parsed at this time. I will create a bug that will track the fact that the MCSymbol operands can't be parsed yet. llvm-svn: 245737
* MIR Serialization: Use the global value syntax for global value memory operands.Alex Lorenz2015-08-201-1/+4
| | | | | | | | | | | This commit modifies the serialization syntax so that the global IR values in machine memory operands use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. The unnamed global IR values are handled by this commit as well, as the existing global value parsing method can parse the unnamed globals already. llvm-svn: 245527
* MIR Serialization: Change syntax for the call entry pseudo source values.Alex Lorenz2015-08-201-1/+2
| | | | | | | | | | | | The global IR values in machine memory operands should use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. However, the global value call entry pseudo source values use the global value syntax already. Therefore, the syntax for the call entry pseudo source values has to be changed so that the global values and call entry global value PSVs can be parsed without ambiguities. llvm-svn: 245526
* Fix test failure introduced by r245521.Alex Lorenz2015-08-191-0/+6
| | | | | | | | | Machine memory operands can contain pointer values that are constants, and the 'getLocalSlot' method requires non-constant values. The constant pointer values will have to be serialized in a different patch. llvm-svn: 245523
* MIR Serialization: Serialize unnamed local IR values in memory operands.Alex Lorenz2015-08-191-2/+2
| | | | llvm-svn: 245521
* MIR Printer: Extract the code that prints IR slots to a separate function. NFC.Alex Lorenz2015-08-191-4/+8
| | | | | | This code can be reused when printing references to unnamed local IR values. llvm-svn: 245519
* MIR Serialization: Serialize instruction's register ties.Alex Lorenz2015-08-191-5/+24
| | | | | | | | This commit serializes the machine instruction's register operand ties. The ties are printed out only when the instructon has register ties that are different from the ties that are specified in the instruction's description. llvm-svn: 245482
* MIR Serialization: Serialize defined registers that require 'def' register flag.Alex Lorenz2015-08-191-3/+8
| | | | | | | | | The defined registers are already serialized - they are represented by placing them before the '=' in a machine instruction. However, certain instructions like INLINEASM can have defined register operands after the '=', so this commit introduces the 'def' register flag for such operands. llvm-svn: 245480
* MIR Serialization: Serialize MMI's variable debug information.Alex Lorenz2015-08-191-2/+27
| | | | llvm-svn: 245396
* MIR Serialization: Serialize the operand's bit mask target flags.Alex Lorenz2015-08-181-5/+37
| | | | | | | | | This commit adds support for bit mask target flag serialization to the MIR printer and the MIR parser. It also adds support for the machine operand's target flag serialization to the AArch64 target. Reviewers: Duncan P. N. Exon Smith llvm-svn: 245383
* MIR Serialization: Serialize the frame information's stack protector index.Alex Lorenz2015-08-181-2/+11
| | | | llvm-svn: 245372
* MIR Serialization: Serialize the local offsets for the stack objects.Alex Lorenz2015-08-171-0/+9
| | | | llvm-svn: 245249
* MIR Serialization: Serialize the memory operand's range metadata node.Alex Lorenz2015-08-171-1/+4
| | | | llvm-svn: 245247
* MIR Serialization: Serialize the memory operand's noalias metadata node.Alex Lorenz2015-08-171-1/+4
| | | | llvm-svn: 245246
* MIR Serialization: Serialize the memory operand's alias scope metadata node.Alex Lorenz2015-08-171-1/+4
| | | | llvm-svn: 245245
* MIR Serialization: Serialize the memory operand's TBAA metadata node.Alex Lorenz2015-08-171-1/+8
| | | | llvm-svn: 245244
* MIR Serialization: Serialize the '.cfi_same_value' CFI directive.Alex Lorenz2015-08-141-0/+6
| | | | llvm-svn: 245103
* MIR Serialization: Serialize the external symbol call entry pseudo sourceAlex Lorenz2015-08-141-3/+4
| | | | | | values. llvm-svn: 245098
* MIR Serialization: Serialize the global value call entry pseudo source values.Alex Lorenz2015-08-141-0/+4
| | | | llvm-svn: 245097
* MIR Serialization: Serialize the 'internal' register operand flag.Alex Lorenz2015-08-141-1/+3
| | | | llvm-svn: 245085
* MIR Serialization: Serialize the bundled machine instructions.Alex Lorenz2015-08-141-3/+14
| | | | llvm-svn: 245082
* MIR Serialization: Change MIR syntax - use custom syntax for MBBs.Alex Lorenz2015-08-131-49/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit modifies the way the machine basic blocks are serialized - now the machine basic blocks are serialized using a custom syntax instead of relying on YAML primitives. Instead of using YAML mappings to represent the individual machine basic blocks in a machine function's body, the new syntax uses a single YAML block scalar which contains all of the machine basic blocks and instructions for that function. This is an example of a function's body that uses the old syntax: body: - id: 0 name: entry instructions: - '%eax = MOV32r0 implicit-def %eflags' - 'RETQ %eax' ... The same body is now written like this: body: | bb.0.entry: %eax = MOV32r0 implicit-def %eflags RETQ %eax ... This syntax change is motivated by the fact that the bundled machine instructions didn't map that well to the old syntax which was using a single YAML sequence to store all of the machine instructions in a block. The bundled machine instructions internally use flags like BundledPred and BundledSucc to determine the bundles, and serializing them as MI flags using the old syntax would have had a negative impact on the readability and the ease of editing for MIR files. The new syntax allows me to serialize the bundled machine instructions using a block construct without relying on the internal flags, for example: BUNDLE implicit-def dead %itstate, implicit-def %s1 ... { t2IT 1, 24, implicit-def %itstate %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate } This commit also converts the MIR testcases to the new syntax. I developed a script that can convert from the old syntax to the new one. I will post the script on the llvm-commits mailing list in the thread for this commit. llvm-svn: 244982
* MIR Serialization: Serialize the fixed stack pseudo source values.Alex Lorenz2015-08-121-0/+4
| | | | llvm-svn: 244816
* MIR Serialization: Serialize the jump table pseudo source values.Alex Lorenz2015-08-121-0/+3
| | | | llvm-svn: 244813
* MIR Serialization: Serialize the GOT pseudo source values.Alex Lorenz2015-08-121-0/+3
| | | | llvm-svn: 244809
* MIR Serialization: Serialize the stack pseudo source values.Alex Lorenz2015-08-121-0/+3
| | | | llvm-svn: 244806
* MIR Serialization: Serialize the constant pool pseudo source values.Alex Lorenz2015-08-121-2/+14
| | | | llvm-svn: 244803
* MIR Serialization: Serialize UsedPhysRegMask from the machine register info.Alex Lorenz2015-08-111-0/+14
| | | | | | | | | | | | This commit serializes the UsedPhysRegMask register mask from the machine register information class. The mask is serialized as an inverted 'calleeSavedRegisters' mask to keep the output minimal. This commit also allows the MIR parser to infer this mask from the register mask operands if the machine function doesn't specify it. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244548
* MIR Serialization: Serialize the liveout register mask machine operands.Alex Lorenz2015-08-101-0/+15
| | | | llvm-svn: 244529
* MIR Serialization: Serialize the base alignment for the machine memory operands.Alex Lorenz2015-08-071-1/+2
| | | | llvm-svn: 244357
* MIR Serialization: Serialize the offsets for the machine memory operands.Alex Lorenz2015-08-071-0/+1
| | | | llvm-svn: 244356
* MIR Serialization: Fix serialization of unnamed IR block references.Alex Lorenz2015-08-061-1/+10
| | | | | | | | The block address machine operands can reference IR blocks in other functions. This commit fixes a bug where the references to unnamed IR blocks in other functions weren't serialized correctly. llvm-svn: 244299
* MIR Serialization: Serialize the 'invariant' machine memory operand flag.Alex Lorenz2015-08-061-1/+3
| | | | llvm-svn: 244230
* MIR Serialization: Serialize the 'non-temporal' machine memory operand flag.Alex Lorenz2015-08-061-0/+2
| | | | llvm-svn: 244228
* MIR Serialization: Initial serialization of the machine operand target flags.Alex Lorenz2015-08-061-6/+28
| | | | | | | | | | | | This commit implements the initial serialization of the machine operand target flags. It extends the 'TargetInstrInfo' class to add two new methods that help to provide text based serialization for the target flags. This commit can serialize only the X86 target flags, and the target flags for the other targets will be serialized in the follow-up commits. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244185
* MIR Serialization: Serialize the machine operand's offset.Alex Lorenz2015-08-051-4/+20
| | | | | | | This commit serializes the offset for the following operands: target index, global address, external symbol, constant pool index, and block address. llvm-svn: 244157
* MIR Serialization: Serialize the typed immediate integer machine operands.Alex Lorenz2015-08-051-0/+3
| | | | llvm-svn: 244098
* MIR Serialization: Serialize the 'early-clobber' register operand flag.Alex Lorenz2015-08-051-0/+2
| | | | llvm-svn: 244075
* MIR Serialization: Serialize the 'debug-use' register operand flag.Alex Lorenz2015-08-051-0/+2
| | | | llvm-svn: 244071
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