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* MIR Serialization: Serialize the external symbol machine operands.Alex Lorenz2015-07-211-0/+15
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 242806
* MIR Serialization: Initial serialization of machine constant pools.Alex Lorenz2015-07-201-0/+17
| | | | | | | | | | This commit implements the initial serialization of machine constant pools and the constant pool index machine operands. The constant pool is serialized using a YAML sequence of YAML mappings that represent the constant values. The target-specific constant pool items aren't serialized by this commit. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242707
* MIR Parser: Add support for quoted named global value operands.Alex Lorenz2015-07-201-3/+22
| | | | | | | | | | This commit extends the machine instruction lexer and implements support for the quoted global value tokens. With this change the syntax for the global value identifier tokens becomes identical to the syntax for the global identifier tokens from the LLVM's assembly language. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242702
* MIR Serialization: Serialize the frame setup machine instruction flag.Alex Lorenz2015-07-171-5/+10
| | | | llvm-svn: 242491
* MIR Serialization: Serialize the frame index machine operands.Alex Lorenz2015-07-161-0/+43
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 242487
* MIR Serialization: Serialize the jump table index operands.Alex Lorenz2015-07-151-0/+17
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 242358
* MIR Serialization: Serialize the machine basic block live in registers.Alex Lorenz2015-07-141-0/+21
| | | | llvm-svn: 242204
* MIR Serialization: Serialize the sub register indices.Alex Lorenz2015-07-131-2/+47
| | | | | | | | This commit serializes the sub register indices from the register machine operands. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242084
* MIR Serialization: Serialize the virtual register operands.Alex Lorenz2015-07-101-0/+12
| | | | | | | | Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D11005 llvm-svn: 241959
* MIR Serialization: Serialize the 'undef' register machine operand flag.Alex Lorenz2015-07-081-1/+5
| | | | llvm-svn: 241762
* MIR Parser: Remove redundant TODO comment. NFC.Alex Lorenz2015-07-081-2/+0
| | | | | | This TODO comment has been redundant since r240474. llvm-svn: 241737
* MIR Serialization: Serialize the 'killed' register machine operand flag.Alex Lorenz2015-07-081-3/+7
| | | | llvm-svn: 241734
* MIR Serialization: Serialize the 'dead' register machine operand flag.Alex Lorenz2015-07-071-1/+6
| | | | llvm-svn: 241624
* MIR Parser: wrap 'MBBSlots' from the MI parsing functions in a struct. NFC.Alex Lorenz2015-07-071-20/+16
| | | | | | | | | | | This commit modifies the interface for the machine instruction parsing functions by wrapping the parameter 'MBBSlots' in a new structure called 'PerFunctionMIParsingState'. This change is useful as in the future I will be able to pass new parameters to the machine instruction parser just by modifying the 'PerFunctionMIParsingState' structure instead of adding a new parameter to each function. llvm-svn: 241607
* MIR Parser: Verify the implicit machine register operands.Alex Lorenz2015-07-071-5/+88
| | | | | | | | | | | | This commit verifies that the parsed machine instructions contain the implicit register operands as specified by the MCInstrDesc. Variadic and call instructions aren't verified. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10781 llvm-svn: 241537
* MIR Serialization: Serialize the implicit register flag.Alex Lorenz2015-07-061-18/+33
| | | | | | | | | | | | | | This commit serializes the implicit flag for the register machine operands. It introduces two new keywords into the machine instruction syntax: 'implicit' and 'implicit-def'. The 'implicit' keyword is used for the implicit register operands, and the 'implicit-def' keyword is used for the register operands that have both the implicit and the define flags set. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10709 llvm-svn: 241519
* MIR Serialization: Serialize MBB successors.Alex Lorenz2015-06-301-2/+31
| | | | | | | | | | | | | This commit implements serialization of the machine basic block successors. It uses a YAML flow sequence that contains strings that have the MBB references. The MBB references in those strings use the same syntax as the MBB machine operands in the machine instruction strings. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10699 llvm-svn: 241093
* MIR Parser: make the machine instruction parsing interface more consistent. NFC.Alex Lorenz2015-06-301-20/+16
| | | | | | | | | This commit refactors the interface for machine instruction parser. It adopts the pattern of returning a bool and passing in the result in the first argument that is used by the other parsing methods for the the method 'parse' and the function 'parseMachineInstr'. llvm-svn: 241085
* MIR Serialization: Serialize the register mask machine operands.Alex Lorenz2015-06-291-1/+39
| | | | | | | | | | | | | | | | | This commit implements serialization of the register mask machine operands. This commit serializes only the call preserved register masks that are defined by a target, it doesn't serialize arbitrary register masks. This commit also extends the TargetRegisterInfo class and TableGen so that the users of TRI can get the list of all the call preserved register masks and their names. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10673 llvm-svn: 240966
* MIR Serialization: Serialize global address machine operands.Alex Lorenz2015-06-261-5/+46
| | | | | | | | | | | | This commit serializes the global address machine operands. This commit doesn't serialize the operand's offset and target flags, it serializes only the global value reference. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10671 llvm-svn: 240851
* MIR Serialization: Serialize machine basic block operands.Alex Lorenz2015-06-261-7/+49
| | | | | | | | | | | | | | | | | | | | | | | | | This commit serializes machine basic block operands. The machine basic block operands use the following syntax: %bb.<id>[.<name>] This commit also modifies the YAML representation for the machine basic blocks - a new, required field 'id' is added to the MBB YAML mapping. The id is used to resolve the MBB references to the actual MBBs. And while the name of the MBB can be included in a MBB reference, this name isn't used to resolve MBB references - as it's possible that multiple MBBs will reference the same BB and thus they will have the same name. If the name is specified, the parser will verify that it is equal to the name of the MBB with the specified id. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10608 llvm-svn: 240792
* MIR Serialization: Serialize the null register operands.Alex Lorenz2015-06-241-0/+6
| | | | | | | | | | | | This commit serializes the null register machine operands. It uses the '_' keyword to represent them, but the parser also allows the '%noreg' named register syntax. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10580 llvm-svn: 240558
* MIR Serialization: Serialize immediate machine operands.Alex Lorenz2015-06-231-0/+14
| | | | | | | | Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10573 llvm-svn: 240481
* MIR Serialization: Serialize physical register machine operands.Alex Lorenz2015-06-231-2/+124
| | | | | | | | | | | This commit introduces functionality that's used to serialize machine operands. Only the physical register operands are serialized by this commit. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10525 llvm-svn: 240425
* MIR Serialization: Introduce a lexer for machine instructions.Alex Lorenz2015-06-221-11/+40
| | | | | | | | | | | | This commit adds a function that tokenizes the string containing the machine instruction. This commit also adds a struct called 'MIToken' which is used to represent the lexer's tokens. Reviewers: Sean Silva Differential Revision: http://reviews.llvm.org/D10521 llvm-svn: 240323
* MIR Serialization: Serialize machine instruction names.Alex Lorenz2015-06-221-0/+106
This commit implements initial machine instruction serialization. It serializes machine instruction names. The instructions are represented using a YAML sequence of string literals and are a part of machine basic block YAML mapping. This commit introduces a class called 'MIParser' which will be used to parse the machine instructions and operands. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10481 llvm-svn: 240295
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