summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/MIRParser/MIParser.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [MIR] Teach the parser how to parse complex types of generic machine ↵Quentin Colombet2016-03-081-14/+29
| | | | | | | | instructions. By complex types, I mean aggregate or vector types. llvm-svn: 262890
* [MIR] Teach the mir parser about types on generic machine instructions.Quentin Colombet2016-03-081-0/+33
| | | | llvm-svn: 262879
* [MIR] Teach the parser how to handle the size of generic virtual registers.Quentin Colombet2016-03-071-8/+36
| | | | llvm-svn: 262862
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper2015-12-051-2/+2
| | | | | | physical register arrays already use this typedef. llvm-svn: 254843
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. (This is the second attempt to submit this patch. The first caused two assertion failures and was reverted. See https://llvm.org/bugs/show_bug.cgi?id=25687) The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254377
* Revert r254348: "Replace all weight-based interfaces in MBB with ↵Hans Wennborg2015-12-011-2/+1
| | | | | | | | | | probability-based interfaces, and update all uses of old interfaces." and the follow-up r254356: "Fix a bug in MachineBlockPlacement that may cause assertion failure during BranchProbability construction." Asserts were firing in Chromium builds. See PR25687. llvm-svn: 254366
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254348
* Fix PR 24724 - The implicit register verifier shouldn't assume certain operandAlex Lorenz2015-09-101-39/+16
| | | | | | | | | | order. The implicit register verifier in the MIR parser should only check if the instruction's default implicit operands are present in the instruction. It should not check the order in which they occur. llvm-svn: 247283
* [WinEH] Add some support for code generating catchpadReid Kleckner2015-08-271-1/+1
| | | | | | | We can now run 32-bit programs with empty catch bodies. The next step is to change PEI so that we get funclet prologues and epilogues. llvm-svn: 246235
* MIR Serialization: Serialize the pointer IR expression values in the machineAlex Lorenz2015-08-211-2/+11
| | | | | | memory operands. llvm-svn: 245745
* MIRParser: Split the 'parseIRConstant' method into two methods. NFC.Alex Lorenz2015-08-211-3/+12
| | | | | | | One variant of this method can be reused when parsing the quoted IR pointer expressions in the machine memory operands. llvm-svn: 245743
* MIR Serialization: Print MCSymbol operands.Alex Lorenz2015-08-211-1/+1
| | | | | | | | This commit allows the MIR printer to print the MCSymbol machine operands. Unfortunately they can't be parsed at this time. I will create a bug that will track the fact that the MCSymbol operands can't be parsed yet. llvm-svn: 245737
* MIR Serialization: Use the global value syntax for global value memory operands.Alex Lorenz2015-08-201-4/+11
| | | | | | | | | | | This commit modifies the serialization syntax so that the global IR values in machine memory operands use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. The unnamed global IR values are handled by this commit as well, as the existing global value parsing method can parse the unnamed globals already. llvm-svn: 245527
* MIR Serialization: Change syntax for the call entry pseudo source values.Alex Lorenz2015-08-201-13/+20
| | | | | | | | | | | | The global IR values in machine memory operands should use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. However, the global value call entry pseudo source values use the global value syntax already. Therefore, the syntax for the call entry pseudo source values has to be changed so that the global values and call entry global value PSVs can be parsed without ambiguities. llvm-svn: 245526
* MIR Serialization: Serialize unnamed local IR values in memory operands.Alex Lorenz2015-08-191-4/+45
| | | | llvm-svn: 245521
* MIR Parser: parseIRValue should take in a constant pointer. NFC.Alex Lorenz2015-08-191-3/+3
| | | | llvm-svn: 245520
* MIR Parser: Rename 'MachineOperandWithLocation' to 'ParsedMachineOperand'. NFC.Alex Lorenz2015-08-191-14/+13
| | | | | | | Besides storing the operand's source range, this structure now stores other attributes as well, so the name should reflect this fact. llvm-svn: 245483
* MIR Serialization: Serialize instruction's register ties.Alex Lorenz2015-08-191-14/+93
| | | | | | | | This commit serializes the machine instruction's register operand ties. The ties are printed out only when the instructon has register ties that are different from the ties that are specified in the instruction's description. llvm-svn: 245482
* MIR Serialization: Serialize defined registers that require 'def' register flag.Alex Lorenz2015-08-191-0/+4
| | | | | | | | | The defined registers are already serialized - they are represented by placing them before the '=' in a machine instruction. However, certain instructions like INLINEASM can have defined register operands after the '=', so this commit introduces the 'def' register flag for such operands. llvm-svn: 245480
* MIR Serialization: Serialize MMI's variable debug information.Alex Lorenz2015-08-191-0/+18
| | | | llvm-svn: 245396
* MIR Parser: Return true on error when parsing standalone registers.Alex Lorenz2015-08-181-2/+2
| | | | llvm-svn: 245384
* MIR Serialization: Serialize the operand's bit mask target flags.Alex Lorenz2015-08-181-4/+47
| | | | | | | | | This commit adds support for bit mask target flag serialization to the MIR printer and the MIR parser. It also adds support for the machine operand's target flag serialization to the AArch64 target. Reviewers: Duncan P. N. Exon Smith llvm-svn: 245383
* MIR Serialization: Serialize the frame information's stack protector index.Alex Lorenz2015-08-181-0/+21
| | | | llvm-svn: 245372
* MIR Parser: Extract the code that parses stack object references into a newAlex Lorenz2015-08-181-2/+11
| | | | | | | | | | method. This commit extracts the code that parses the stack object references into a new method named 'parseStackFrameIndex', so that it can be reused when parsing standalone stack object references. llvm-svn: 245370
* MIR Parser: Implicit register verifier should accept unexpected implicitAlex Lorenz2015-08-181-0/+13
| | | | | | subregister operands. llvm-svn: 245315
* MIR Serialization: Serialize the memory operand's range metadata node.Alex Lorenz2015-08-171-4/+10
| | | | llvm-svn: 245247
* MIR Serialization: Serialize the memory operand's noalias metadata node.Alex Lorenz2015-08-171-2/+7
| | | | llvm-svn: 245246
* MIR Serialization: Serialize the memory operand's alias scope metadata node.Alex Lorenz2015-08-171-2/+6
| | | | llvm-svn: 245245
* MIR Serialization: Serialize the memory operand's TBAA metadata node.Alex Lorenz2015-08-171-8/+20
| | | | llvm-svn: 245244
* MIR Serialization: Serialize the '.cfi_same_value' CFI directive.Alex Lorenz2015-08-141-0/+7
| | | | llvm-svn: 245103
* MIR Serialization: Serialize the external symbol call entry pseudo sourceAlex Lorenz2015-08-141-2/+6
| | | | | | values. llvm-svn: 245098
* MIR Serialization: Serialize the global value call entry pseudo source values.Alex Lorenz2015-08-141-1/+10
| | | | llvm-svn: 245097
* MIR Serialization: Serialize the 'internal' register operand flag.Alex Lorenz2015-08-141-2/+6
| | | | llvm-svn: 245085
* MIR Serialization: Serialize the bundled machine instructions.Alex Lorenz2015-08-141-7/+43
| | | | llvm-svn: 245082
* MIR Serialization: Change MIR syntax - use custom syntax for MBBs.Alex Lorenz2015-08-131-42/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit modifies the way the machine basic blocks are serialized - now the machine basic blocks are serialized using a custom syntax instead of relying on YAML primitives. Instead of using YAML mappings to represent the individual machine basic blocks in a machine function's body, the new syntax uses a single YAML block scalar which contains all of the machine basic blocks and instructions for that function. This is an example of a function's body that uses the old syntax: body: - id: 0 name: entry instructions: - '%eax = MOV32r0 implicit-def %eflags' - 'RETQ %eax' ... The same body is now written like this: body: | bb.0.entry: %eax = MOV32r0 implicit-def %eflags RETQ %eax ... This syntax change is motivated by the fact that the bundled machine instructions didn't map that well to the old syntax which was using a single YAML sequence to store all of the machine instructions in a block. The bundled machine instructions internally use flags like BundledPred and BundledSucc to determine the bundles, and serializing them as MI flags using the old syntax would have had a negative impact on the readability and the ease of editing for MIR files. The new syntax allows me to serialize the bundled machine instructions using a block construct without relying on the internal flags, for example: BUNDLE implicit-def dead %itstate, implicit-def %s1 ... { t2IT 1, 24, implicit-def %itstate %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate } This commit also converts the MIR testcases to the new syntax. I developed a script that can convert from the old syntax to the new one. I will post the script on the llvm-commits mailing list in the thread for this commit. llvm-svn: 244982
* MIR Parser: Don't allow negative alignments for memory operands.Alex Lorenz2015-08-131-1/+1
| | | | llvm-svn: 244953
* MIR Parser: Extract the code that parses the alignment into a new method. NFC.Alex Lorenz2015-08-131-5/+13
| | | | | | | | This commit extracts the code that parses the memory operand's alignment into a new method named 'parseAlignment' so that it can be reused when parsing the basic block's alignment attribute. llvm-svn: 244945
* MIR Parser: Allow the MI IR references to reference global values.Alex Lorenz2015-08-121-0/+3
| | | | | | | This commit fixes a bug where MI parser couldn't resolve the named IR references that referenced named global values. llvm-svn: 244817
* MIR Serialization: Serialize the fixed stack pseudo source values.Alex Lorenz2015-08-121-1/+10
| | | | llvm-svn: 244816
* MIR Parser: Move the parsing of fixed stack object indices into new method. NFCAlex Lorenz2015-08-121-2/+11
| | | | | | | | | This commit moves the code that parses the frame indices for the fixed stack objects from the method 'parseFixedStackObjectOperand' to a new method named 'parseFixedStackFrameIndex', so that it can be reused when parsing fixed stack pseudo source values. llvm-svn: 244814
* MIR Serialization: Serialize the jump table pseudo source values.Alex Lorenz2015-08-121-1/+4
| | | | llvm-svn: 244813
* MIR Serialization: Serialize the GOT pseudo source values.Alex Lorenz2015-08-121-1/+5
| | | | llvm-svn: 244809
* MIR Serialization: Serialize the stack pseudo source values.Alex Lorenz2015-08-121-1/+4
| | | | llvm-svn: 244806
* MIR Serialization: Serialize the constant pool pseudo source values.Alex Lorenz2015-08-121-14/+44
| | | | llvm-svn: 244803
* MIR Serialization: Serialize the liveout register mask machine operands.Alex Lorenz2015-08-101-0/+30
| | | | llvm-svn: 244529
* MIR Serialization: Serialize the base alignment for the machine memory operands.Alex Lorenz2015-08-071-3/+14
| | | | llvm-svn: 244357
* MIR Serialization: Serialize the offsets for the machine memory operands.Alex Lorenz2015-08-071-1/+5
| | | | llvm-svn: 244356
* MIR Parser: Extract the parsing of the operand's offset into a new method. NFC.Alex Lorenz2015-08-071-2/+10
| | | | | | | | This commit extract the code that parses the 64-bit offset from the method 'parseOperandsOffset' to a new method 'parseOffset' so that we can reuse it when parsing the offset for the machine memory operands. llvm-svn: 244355
* MIR Serialization: Fix serialization of unnamed IR block references.Alex Lorenz2015-08-061-10/+23
| | | | | | | | The block address machine operands can reference IR blocks in other functions. This commit fixes a bug where the references to unnamed IR blocks in other functions weren't serialized correctly. llvm-svn: 244299
* MIR Parser: Simplify the token's string value handling.Alex Lorenz2015-08-061-9/+7
| | | | | | | | | | | | | | | | | This commit removes the 'StringOffset' and 'HasStringValue' fields from the MIToken struct and simplifies the 'stringValue' method which now returns the new 'StringValue' field. This commit also adopts a different way of initializing the lexed tokens - instead of constructing a new MIToken instance, the lexer resets the old token using the new 'reset' method and sets its attributes using the new 'setStringValue', 'setOwnedStringValue', and 'setIntegerValue' methods. Reviewers: Sean Silva Differential Revision: http://reviews.llvm.org/D11792 llvm-svn: 244295
OpenPOWER on IntegriCloud