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* Modify df_iterator to support post-order actionsDavid Callahan2016-10-051-1/+1
| | | | | | | | | | | | Summary: This makes a change to the state used to maintain visited information for depth first iterator. We know assume a method "completed(...)" which is called after all children of a node have been visited. In all existing cases, this method does nothing so this patch has no functional changes. It will however allow a client to distinguish back from cross edges in a DFS tree. Reviewers: nadav, mehdi_amini, dberlin Subscribers: MatzeB, mzolotukhin, twoh, freik, llvm-commits Differential Revision: https://reviews.llvm.org/D25191 llvm-svn: 283391
* CodeGen: Use MachineInstr& in LiveVariables API, NFCDuncan P. N. Exon Smith2016-07-011-24/+24
| | | | | | | | | Change all the methods in LiveVariables that expect non-null MachineInstr* to take MachineInstr& and update the call sites. This clarifies the API, and designs away a class of iterator to pointer implicit conversions. llvm-svn: 274319
* CodeGen: Use range-based for in LiveVariables, NFCDuncan P. N. Exon Smith2016-06-301-6/+4
| | | | | | | Avoid an implicit iterator to pointer conversion in LiveVariables::runOnBlock by switching to a range-based for. llvm-svn: 274297
* LiveVariables: Fix typo and shorten commentMatthias Braun2016-03-291-4/+2
| | | | llvm-svn: 264768
* LiveVariables: Do not remove dead flags from vreg operandsMatthias Braun2016-03-291-3/+8
| | | | | | | Also add a FIXME comment on why Mips RDDSP causes bogus dead flags to be added which LiveVariables cleans up by accident. llvm-svn: 264695
* Annotate dump() methods with LLVM_DUMP_METHOD, addressing Richard Smith ↵Yaron Keren2016-01-291-1/+1
| | | | | | | | r259192 post commit comment. clang part in r259232, this is the LLVM part of the patch. llvm-svn: 259240
* LiveVariables should not clobber MachineOperand::IsDead, ::IsKill on ↵Matthias Braun2015-11-241-2/+6
| | | | | | | | | | reserved physical registers Patch by Nick Johnson <Nicholas.Paul.Johnson@deshawresearch.com> Differential Revision: http://reviews.llvm.org/D14875 llvm-svn: 254012
* CodeGen: Remove more ilist iterator implicit conversions, NFCDuncan P. N. Exon Smith2015-10-091-1/+1
| | | | llvm-svn: 249879
* Save LaneMask with livein registersMatthias Braun2015-09-091-6/+6
| | | | | | | | | | | | | | | | | With subregister liveness enabled we can detect the case where only parts of a register are live in, this is expressed as a 32bit lanemask. The current code only keeps registers in the live-in list and therefore enumerated all subregisters affected by the lanemask. This turned out to be too conservative as the subregister may also cover additional parts of the lanemask which are not live. Expressing a given lanemask by enumerating a minimum set of subregisters is computationally expensive so the best solution is to simply change the live-in list to store the lanemasks as well. This will reduce memory usage for targets using subregister liveness and slightly increase it for other targets Differential Revision: http://reviews.llvm.org/D12442 llvm-svn: 247171
* [WinEH] Add some support for code generating catchpadReid Kleckner2015-08-271-1/+1
| | | | | | | We can now run 32-bit programs with empty catch bodies. The next step is to change PEI so that we get funclet prologues and epilogues. llvm-svn: 246235
* MachineBasicBlock: Add liveins() method returning an iterator_rangeMatthias Braun2015-08-241-9/+6
| | | | llvm-svn: 245895
* [LiveVariables] Improve isLiveOut runtime performances. NFC.Arnaud A. de Grandmaison2015-06-111-31/+8
| | | | | | | | | | | | On large goto table based interpreters, where phi nodes can have (very) large fan-ins, isLiveOut exhibited poor performances: about 40% of the full codegen time was spent in PHIElim, sorting MachineBasicBlock addresses. This patch improve the performances for such cases, and does not show compile time regressions on the LNT, at bootstrap (llvm+clang+lldb) or any other benchmarks we have in-house. llvm-svn: 239510
* Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.Benjamin Kramer2015-03-231-0/+1
| | | | llvm-svn: 232998
* Remove unnecessary TargetMachine.h includes.Eric Christopher2014-10-141-1/+0
| | | | llvm-svn: 219672
* CodeGen/LiveVariables: use vector::assign()Dylan Noblesmith2014-08-261-8/+4
| | | | | | Address review comments. llvm-svn: 216426
* CodeGen/LiveVariables: hoist out code in nested loopsDylan Noblesmith2014-08-251-110/+121
| | | | | | This makes runOnMachineFunction vastly more readable. llvm-svn: 216368
* CodeGen/LiveVariables: switch to std::vectorDylan Noblesmith2014-08-251-11/+13
| | | | | | No functionality change. llvm-svn: 216367
* Use range based for loops to avoid needing to re-mention SmallPtrSet size.Craig Topper2014-08-241-5/+1
| | | | llvm-svn: 216351
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-1/+1
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-1/+1
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Convert more loops to range-based equivalentsAlexey Samsonov2014-04-301-6/+8
| | | | llvm-svn: 207714
* Convert several loops over MachineFunction basic blocks to range-based loopsAlexey Samsonov2014-04-301-3/+2
| | | | llvm-svn: 207683
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-13/+13
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-111-2/+2
| | | | | | size. llvm-svn: 186098
* Use SmallVectorImpl instead of SmallVector for iterators and references to ↵Craig Topper2013-07-031-2/+2
| | | | | | avoid specifying the vector size unnecessarily. llvm-svn: 185512
* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-221-15/+14
| | | | llvm-svn: 182526
* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-051-23/+0
| | | | | | | Now that return value registers are return instruction uses, there is no need for special treatment of return blocks. llvm-svn: 174416
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-5/+5
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-151-4/+2
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. llvm-svn: 165983
* Release build: guard dump functions withManman Ren2012-09-111-1/+1
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* LiveVariables: Compute a set of defs and kills to speed up updating LV ↵Benjamin Kramer2012-09-091-4/+30
| | | | | | | | | | | | | | | during critical edge splitting. Previously we checked if the register is def'd in a block via the def/use list a nd walked the list of kills to check if the register is killed in a block. Both of these checks can be made much cheaper by walking the block first and recording all defs and kills. This reduces the compile time of the test case from PR13651 from 40s to 15s at -O2. The compile time is still dominated by LV updating but now the main culprit is SparseBitVector's slowness. llvm-svn: 163478
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+2
| | | | | | No functional change. llvm-svn: 163339
* Teach LiveVariables to handle <undef> operands.Jakob Stoklund Olesen2012-06-231-3/+5
| | | | | | | | It's simple: Don't treat <undef> operands as uses, and don't assume a virtual register has a defining instruction unless a real use has been seen. llvm-svn: 159061
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-32/+29
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Fix typo.Lang Hames2012-04-011-1/+1
| | | | llvm-svn: 153846
* Assert on SSA errors in LiveVariables.Jakob Stoklund Olesen2012-03-091-0/+1
| | | | | | All uses of a virtual register must be dominated by its def. llvm-svn: 152449
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-17/+17
| | | | | | static data size. llvm-svn: 152016
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-101-0/+8
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* whitespaceAndrew Trick2012-02-031-3/+3
| | | | llvm-svn: 149671
* Fix an obvious typo.Evan Cheng2012-01-211-1/+1
| | | | llvm-svn: 148622
* Handle register masks in LiveVariables.Jakob Stoklund Olesen2012-01-211-0/+30
| | | | | | | | | | | A register mask operand kills any live physreg that isn't preserved. Unlike an implicit-def operand, the clobbered physregs are never live afterwards. This means LiveVariables has to track a much smaller number of live physregs, and it should spend much less time in addRegisterDead(). llvm-svn: 148609
* Delete an unused member variable.Jakob Stoklund Olesen2012-01-201-1/+0
| | | | llvm-svn: 148594
* After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng2012-01-141-6/+22
| | | | | | | | | | | | | | | | | | | live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 llvm-svn: 148168
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-2/+2
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-1/+1
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-121-1/+1
| | | | | | when building with assertions disabled. llvm-svn: 137460
* Reduce vector reallocations.Benjamin Kramer2011-03-081-4/+2
| | | | llvm-svn: 127254
* Use an IndexedMap for LiveVariables::VirtRegInfo.Jakob Stoklund Olesen2011-01-081-25/+10
| | | | | | | | Provide MRI::getNumVirtRegs() and TRI::index2VirtReg() functions to allow iteration over virtual registers without depending on the representation of virtual register numbers. llvm-svn: 123098
* Begin adding static dependence information to passes, which will allow us toOwen Anderson2010-10-121-1/+4
| | | | | | | | | perform initialization without static constructors AND without explicit initialization by the client. For the moment, passes are required to initialize both their (potential) dependencies and any passes they preserve. I hope to be able to relax the latter requirement in the future. llvm-svn: 116334
* Now with fewer extraneous semicolons!Owen Anderson2010-10-071-1/+1
| | | | llvm-svn: 115996
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