summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* The Indexes Patch.Lang Hames2009-11-031-635/+158
| | | | | | | | | | | | | | | | This introduces a new pass, SlotIndexes, which is responsible for numbering instructions for register allocation (and other clients). SlotIndexes numbering is designed to match the existing scheme, so this patch should not cause any changes in the generated code. For consistency, and to avoid naming confusion, LiveIndex has been renamed SlotIndex. The processImplicitDefs method of the LiveIntervals analysis has been moved into its own pass so that it can be run prior to SlotIndexes. This was necessary to match the existing numbering scheme. llvm-svn: 85979
* Trim unnecessary includes.Evan Cheng2009-10-201-1/+0
| | | | llvm-svn: 84597
* If the physical register being spilled does not have an interval, spill its ↵Evan Cheng2009-10-201-5/+21
| | | | | | sub-registers instead. llvm-svn: 84586
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-091-94/+5
| | | | | | | | | | | | | | is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. llvm-svn: 83687
* isTriviallyReMaterializable checks theDan Gohman2009-10-091-2/+1
| | | | | | | TargetInstrDesc::isRematerializable flag, so it isn't necessary to do this check in its callers. llvm-svn: 83671
* Replace some code for aggressive-remat with MachineInstr::isInvariantLoad, andDan Gohman2009-10-071-23/+28
| | | | | | teach it how to recognize invariant physical registers. llvm-svn: 83476
* Oops. Renamed remaining MachineInstrIndex references.Lang Hames2009-10-031-8/+8
| | | | llvm-svn: 83255
* Renamed MachineInstrIndex to LiveIndex.Lang Hames2009-10-031-92/+92
| | | | llvm-svn: 83254
* Remove unused variable.Daniel Dunbar2009-09-251-2/+0
| | | | llvm-svn: 82821
* Simplify a few more uses of reg_iterator.Dan Gohman2009-09-251-4/+2
| | | | llvm-svn: 82812
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-5/+6
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Fix PR5024. LiveVariables physical register defs should *commit* only after allEvan Cheng2009-09-231-0/+4
| | | | | | | | of the defs are processed. Also fix a implicit_def propagation bug: a implicit_def of a physical register should be applied to uses of the sub-registers. llvm-svn: 82616
* Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an ↵Evan Cheng2009-09-211-10/+23
| | | | | | implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information. llvm-svn: 82436
* When computing live intervals for earlyclobber operands,Dale Johannesen2009-09-201-3/+16
| | | | | | | | | | we pushed the beginning of the interval back 1, so the interval would overlap with inputs that die. We were also pushing the end of the interval back 1, though, which means the earlyclobber didn't overlap with other output operands. Don't do this. PR 4964. llvm-svn: 82342
* Fix -Asserts warning.Daniel Dunbar2009-09-151-1/+2
| | | | llvm-svn: 81909
* Another try at early partial coalescing. Identity phi source copies (their ↵Evan Cheng2009-09-151-58/+56
| | | | | | | | sources are defined by phi join def) are coalesced. And the phi join copy is backward copy propagated into the other copies. Still miscompiling some tests. :-( llvm-svn: 81849
* Add early coalescing to liveintervals. This is work in progress and is known ↵Evan Cheng2009-09-141-24/+164
| | | | | | | | to miscompute some tests. Read it at your own rish, I have aged 10 year while writing this. The gist of this is if source of some of the copies that feed into a phi join is defined by the phi join, we'd like to eliminate them. However, if any of the non-identity source overlaps the live interval of the phi join then the coalescer won't be able to coalesce them. The early coalescer's job is to eliminate the identity copies by partially-coalescing the two live intervals. llvm-svn: 81796
* Moved some more index operations over to LiveIntervals.Lang Hames2009-09-121-50/+50
| | | | llvm-svn: 81605
* 80 col violations.Evan Cheng2009-09-121-5/+9
| | | | llvm-svn: 81598
* Replaces uses of unsigned for indexes in LiveInterval and VNInfo withLang Hames2009-09-041-163/+186
| | | | | | | | a new class, MachineInstrIndex, which hides arithmetic details from most clients. This is a step towards allowing the register allocator to update/insert code during allocation. llvm-svn: 81040
* Change Pass::print to take a raw ostream instead of std::ostream,Chris Lattner2009-08-231-2/+1
| | | | | | update all code that this affects. llvm-svn: 79830
* remove various std::ostream version of printing methods fromChris Lattner2009-08-231-6/+8
| | | | | | | | MachineInstr and MachineOperand. This required eliminating a bunch of stuff that was using DOUT, I hope that bill doesn't mind me stealing his fun. ;-) llvm-svn: 79813
* remove a dead class.Chris Lattner2009-08-231-5/+0
| | | | llvm-svn: 79795
* Convert DOUT to DEBUG(errs()...).Bill Wendling2009-08-221-50/+76
| | | | llvm-svn: 79752
* Modified VNInfo. The "copy" member is now a union which holds the copy for a ↵Lang Hames2009-08-101-10/+10
| | | | | | register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. llvm-svn: 78620
* Turn some insert_subreg, extract_subreg, subreg_to_reg into implicit_defs.Evan Cheng2009-08-051-5/+27
| | | | llvm-svn: 78151
* Re-apply LiveInterval index dumping patch, with fixes suggested by BillDavid Greene2009-08-031-0/+6
| | | | | | and others. llvm-svn: 78003
* Use setPreservesAll and setPreservesCFG in CodeGen passes.Dan Gohman2009-07-311-0/+1
| | | | llvm-svn: 77754
* More migration to raw_ostream, the water has dried up around the iostream hole.Daniel Dunbar2009-07-251-5/+5
| | | | | | | | | | - Some clients which used DOUT have moved to DEBUG. We are deprecating the "magic" DOUT behavior which avoided calling printing functions when the statement was disabled. In addition to being unnecessary magic, it had the downside of leaving code in -Asserts builds, and of hiding potentially unnecessary computations. llvm-svn: 77019
* Move to raw_ostream.Daniel Dunbar2009-07-241-2/+2
| | | | llvm-svn: 76963
* Constify the key in Mi2IndexMap.David Greene2009-07-221-1/+1
| | | | llvm-svn: 76801
* revert r76602, 76603, and r76615, pending design discussions.Chris Lattner2009-07-211-2/+9
| | | | llvm-svn: 76646
* Prefix IR dumps with LiveInterval indices when possible. This turnsDavid Greene2009-07-211-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this: %ESI<def> = MOV32rr %EDI<kill> ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use> %reg1027<def> = MOVZX64rr32 %ESI %reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead> %reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead> %RDI<def> = MOV64rr %RSP %RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead> %RSP<def> = MOV64rr %RDI into this: 4 %reg1024<def> = MOV32rr %EDI<kill> 12 ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use> 20 %reg1025<def> = MOVZX64rr32 %reg1024 28 %reg1026<def> = MOV64rr %reg1025<kill> 36 %reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead> 44 %reg1027<def> = MOV64rr %reg1026<kill> 52 %reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead> 60 %reg1028<def> = MOV64rr %RSP 68 %reg1029<def> = MOV64rr %reg1028<kill> 76 %reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead> 84 %RSP<def> = MOV64rr %reg1029 This helps greatly when debugging register allocation and coalescing problems. llvm-svn: 76615
* Simplify the coalescer (finally!) by making ↵Evan Cheng2009-07-171-33/+44
| | | | | | LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands. llvm-svn: 76223
* Changed my mind. We now allow remat of instructions whose defs have subreg ↵Evan Cheng2009-07-161-5/+0
| | | | | | indices. llvm-svn: 76100
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-1/+6
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-1/+1
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Convert more assert(0)+abort() -> LLVM_UNREACHABLE,Torok Edwin2009-07-111-4/+8
| | | | | | and abort()/exit() -> llvm_report_error(). llvm-svn: 75363
* Avoid compiler warnings if assertions turned off.Duncan Sands2009-07-101-0/+2
| | | | llvm-svn: 75267
* Improved tracking of value number kills. VN kills are now representedLang Hames2009-07-091-18/+76
| | | | | | | | | | | | as an (index,bool) pair. The bool flag records whether the kill is a PHI kill or not. This code will be used to enable splitting of live intervals containing PHI-kills. A slight change to live interval weights introduced an extra spill into lsr-code-insertion (outside the critical sections). The test condition has been updated to reflect this. llvm-svn: 75097
* Remove special handling of implicit_def. Fix a couple more bugs in ↵Evan Cheng2009-07-011-24/+51
| | | | | | | | liveintervalanalysis and coalescer handling of implicit_def. Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def. llvm-svn: 74601
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves ↵Evan Cheng2009-07-011-2/+91
| | | | | | the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. llvm-svn: 74580
* Add a bit IsUndef to MachineOperand. This indicates the def / use register ↵Evan Cheng2009-06-301-1/+5
| | | | | | | | | | operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. llvm-svn: 74518
* When doing remat, don't consider uses of non-allocatable physregs. Patch Chris Lattner2009-06-271-0/+4
| | | | | | by Evan. llvm-svn: 74370
* More VNInfo tweaking, plus a little progress on intra-block splitting.Lang Hames2009-06-191-2/+4
| | | | llvm-svn: 73750
* Improved PHI def marking, replaced some gotos with breaks.Lang Hames2009-06-181-5/+7
| | | | llvm-svn: 73727
* VNInfo cleanup.Lang Hames2009-06-171-26/+27
| | | | llvm-svn: 73634
* Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng2009-06-141-1/+1
| | | | | | MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
* Update to in-place spilling framework. Includes live interval scaling and ↵Lang Hames2009-06-021-0/+44
| | | | | | trivial rewriter. llvm-svn: 72729
OpenPOWER on IntegriCloud