summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Don't create a new copy of reserved regs - we already have one handy.Lang Hames2012-02-141-4/+2
| | | | llvm-svn: 150525
* Tighten physical register invariants: Allocatable physical registers canLang Hames2012-02-141-9/+43
| | | | | | only be live in to a block if it is the function entry point or a landing pad. llvm-svn: 150494
* Use convenience function for consistency.Lang Hames2012-02-141-2/+1
| | | | llvm-svn: 150457
* LiveIntervalAnalysis does not depend on MachineLoopInfo.Andrew Trick2012-02-131-4/+2
| | | | llvm-svn: 150411
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-101-14/+2
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* Remove unused 'isAlias' parameter.Lang Hames2012-02-101-8/+3
| | | | llvm-svn: 150224
* Constrain the regmask search space for local live ranges.Jakob Stoklund Olesen2012-02-101-3/+13
| | | | | | | When checking a local live range for interference, restrict the binary search to the single block. llvm-svn: 150220
* Cache basic block boundaries for faster RegMaskSlots access.Jakob Stoklund Olesen2012-02-101-0/+9
| | | | | | | Provide API to get a list of register mask slots and bits in a basic block. llvm-svn: 150219
* Optimize LiveIntervals::intervalIsInOneMBB().Jakob Stoklund Olesen2012-02-101-17/+22
| | | | | | | | No looping and binary searches necessary. Return a pointer to the containing block instead of just a bool. llvm-svn: 150218
* Fix kill flags when moving instructions using LiveIntervals::moveInstr(...).Lang Hames2012-02-091-6/+23
| | | | llvm-svn: 150150
* Remove assertion. Not all use operands are reads.Lang Hames2012-02-091-3/+0
| | | | llvm-svn: 150149
* Keep track of register masks in LiveIntervalAnalysis.Jakob Stoklund Olesen2012-02-081-0/+62
| | | | | | | | | | | | | Build an ordered vector of register mask operands (i.e., calls) when computing live intervals. Provide a checkRegMaskInterference() function that computes a bit mask of usable registers for a live range. This is a quick way of determining of a live range crosses any calls, and restricting it to the callee saved registers if it does. Previously, we had to discover call clobbers for each candidate register independently. llvm-svn: 150077
* Added MachineInstr::isBundled() to check if an instruction is part of a bundle.Andrew Trick2012-02-081-1/+1
| | | | llvm-svn: 150044
* Drop the REDEF_BY_EC VNInfo flag.Jakob Stoklund Olesen2012-02-041-2/+0
| | | | | | | | | | A live range that has an early clobber tied redef now looks like a normal tied redef, except the early clobber def uses the early clobber slot. This is enough to handle any strange interference problems. llvm-svn: 149769
* Correctly terminate a physreg redefined by an early clobber.Jakob Stoklund Olesen2012-02-041-1/+1
| | | | | | | | | | | | | | | | | I don't have a test that fails because of this, but a test case like CodeGen/X86/2009-12-01-EarlyClobberBug.ll exposes the problem. EAX is redefined by a tied early clobber operand on inline asm, and the live range should look like this: %EAX,inf = [48r,64e:0)[64e,80r:1) 0@48r 1@64e Previously, the two values got merged: %EAX,inf = [48r,80r:0) 0@48r With this bug fixed, the REDEF_BY_EC VNInfo flag is no longer needed. llvm-svn: 149768
* Don't store COPY pointers in VNInfo.Jakob Stoklund Olesen2012-02-041-30/+10
| | | | | | | | | | If a value is defined by a COPY, that instuction can easily and cheaply be found by getInstructionFromIndex(VNI->def). This reduces the size of VNInfo from 24 to 16 bytes, and improves llc compile time by 3%. llvm-svn: 149763
* Trim headers.Jakob Stoklund Olesen2012-02-031-8/+0
| | | | llvm-svn: 149722
* Delete some dead code.Jakob Stoklund Olesen2012-02-031-5/+0
| | | | llvm-svn: 149717
* Here's a new one: GCC was complaining about an only-used-in-assertsMatt Beaumont-Gay2012-01-301-2/+2
| | | | | | *function*. Wrap the function in #ifndef NDEBUG. llvm-svn: 149259
* Silence warning about parens for && within ||Lang Hames2012-01-271-1/+1
| | | | llvm-svn: 149152
* Add a "moveInstr" method to LiveIntervals. This can be used to move instructionsLang Hames2012-01-271-0/+201
| | | | | | | | | around within a basic block while maintaining live-intervals. Updated ScheduleTopDownLive in MachineScheduler.cpp to use the moveInstr API when reordering MIs. llvm-svn: 149147
* Don't add live ranges for aliases of physregs that are live in to theLang Hames2012-01-251-5/+0
| | | | | | | | function. They don't appear to be used, and are inconsistent with handling of other physreg intervals (i.e. intervals that are not live-in) where ranges are not inserted for aliases. llvm-svn: 148986
* Always break upon finding a vreg operand (in Release as well as +Asserts). ↵Lang Hames2012-01-251-6/+1
| | | | | | Remove assertion which can no longer trigger. llvm-svn: 148984
* Fixed macro condition.Lang Hames2012-01-181-1/+1
| | | | llvm-svn: 148408
* Exclusively use SplitAnalysis::getLastSplitPoint().Jakob Stoklund Olesen2012-01-111-22/+0
| | | | | | | | | Delete the alternative implementation in LiveIntervalAnalysis. These functions computed the same thing, but SplitAnalysis caches the result. llvm-svn: 147911
* Use the 'regalloc' debug tag for most register allocator tracing.Jakob Stoklund Olesen2012-01-071-1/+1
| | | | llvm-svn: 147725
* Clarified assert text.Lang Hames2012-01-031-1/+1
| | | | llvm-svn: 147471
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Fix early-clobber handling in shrinkToUses.Jakob Stoklund Olesen2011-11-141-12/+8
| | | | | | | | I broke this in r144515, it affected most ARM testers. <rdar://problem/10441389> llvm-svn: 144547
* Use kill slots instead of the previous slot in shrinkToUses.Jakob Stoklund Olesen2011-11-131-13/+14
| | | | | | It's more natural to use the actual end points. llvm-svn: 144515
* Terminate all dead defs at the dead slot instead of the 'next' slot.Jakob Stoklund Olesen2011-11-131-2/+2
| | | | | | | | | | | | | | | | | | | This makes no difference for normal defs, but early clobber dead defs now look like: [Slot_EarlyClobber; Slot_Dead) instead of: [Slot_EarlyClobber; Slot_Register). Live ranges for normal dead defs look like: [Slot_Register; Slot_Dead) as before. llvm-svn: 144512
* Simplify early clobber slots a bit.Jakob Stoklund Olesen2011-11-131-12/+3
| | | | llvm-svn: 144507
* Rename SlotIndexes to match how they are used.Jakob Stoklund Olesen2011-11-131-32/+32
| | | | | | | | | | | | | | | | | | | | The old naming scheme (load/use/def/store) can be traced back to an old linear scan article, but the names don't match how slots are actually used. The load and store slots are not needed after the deferred spill code insertion framework was deleted. The use and def slots don't make any sense because we are using half-open intervals as is customary in C code, but the names suggest closed intervals. In reality, these slots were used to distinguish early-clobber defs from normal defs. The new naming scheme also has 4 slots, but the names match how the slots are really used. This is a purely mechanical renaming, but some of the code makes a lot more sense now. llvm-svn: 144503
* Delete the old spilling framework from LiveIntervalAnalysis.Jakob Stoklund Olesen2011-11-121-1193/+0
| | | | | | This is dead code, all register allocators use InlineSpiller. llvm-svn: 144478
* Add a FIXME.Jakob Stoklund Olesen2011-10-051-0/+4
| | | | | | | | TwoAddressInstructionPass should annotate instructions with <undef> flags when it lower REG_SEQUENCE instructions. LiveIntervals should not be in the business of modifying code (except for kill flags, perhaps). llvm-svn: 141187
* Allow <undef> flags on def operands as well as uses.Jakob Stoklund Olesen2011-10-041-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The <undef> flag says that a MachineOperand doesn't read its register, or doesn't depend on the previous value of its register. A full register def never depends on the previous register value. A partial register def may depend on the previous value if it is intended to update part of a register. For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 The first copy instruction defines the full %vreg10 register with the bits not covered by dsub_0 defined as <undef>. It is not considered a read of %vreg10. The second copy modifies part of %vreg10 while preserving the rest. It has an implicit read of %vreg10. This patch adds a MachineOperand::readsReg() method to determine if an operand reads its register. Previously, this was modelled by adding a full-register <imp-def> operand to the instruction. This approach makes it possible to determine directly from a MachineOperand if it reads its register. No scanning of MI operands is required. llvm-svn: 141124
* Speed up LiveIntervals::shrinkToUse with some caching.Jakob Stoklund Olesen2011-09-151-6/+8
| | | | | | | | | | | | | Blocks with multiple PHI successors only need to go on the worklist once. Use a SmallPtrSet to track the live-out blocks that have already been handled. This is a lot faster than the two live range check we would otherwise do. Also stop recomputing hasPHIKill flags. Like RenumberValues(), it is conservatively correct to leave them in, and they are not used for anything important. llvm-svn: 139792
* Switch extendInBlock() to take a kill slot instead of the last use slot.Jakob Stoklund Olesen2011-09-131-1/+1
| | | | | | | Three out of four clients prefer this interface which is consistent with extendIntervalEndTo() and LiveRangeCalc::extend(). llvm-svn: 139604
* When a physreg is live-in and live through a basic block, make sure its liveJakob Stoklund Olesen2011-04-301-1/+1
| | | | | | | | range covers the entire block. The live range can't be terminated at a random instruction. llvm-svn: 130619
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Don't add live ranges for sub-registers when clobbering a physical register.Jakob Stoklund Olesen2011-04-111-7/+0
| | | | | | | | | Both coalescing and register allocation already check aliases for interference, so these extra segments are only slowing us down. This speeds up both linear scan and the greedy register allocator. llvm-svn: 129283
* Recompute hasPHIKill flags when shrinking live intervals.Jakob Stoklund Olesen2011-04-071-1/+3
| | | | | | PHI values may be deleted, causing the flags to be wrong. This fixes PR9616. llvm-svn: 129092
* Allow coalescing with reserved physregs in certain cases:Jakob Stoklund Olesen2011-04-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When a virtual register has a single value that is defined as a copy of a reserved register, permit that copy to be joined. These virtual register are usually copies of the stack pointer: %vreg75<def> = COPY %ESP; GR32:%vreg75 MOV32mr %vreg75, 1, %noreg, 0, %noreg, %vreg74<kill> MOV32mi %vreg75, 1, %noreg, 8, %noreg, 0 MOV32mi %vreg75<kill>, 1, %noreg, 4, %noreg, 0 CALLpcrel32 ... Coalescing these virtual registers early decreases register pressure. Previously, they were coalesced by RALinScan::attemptTrivialCoalescing after register allocation was completed. The lower register pressure causes the mcinst-lowering-cmp0.ll test case to fail because it depends on linear scan spilling a particular register. I am deleting 2008-08-05-SpillerBug.ll because it is counting the number of instructions emitted, and its revision history shows the 'correct' count being edited many times. llvm-svn: 128845
* lib/CodeGen/LiveIntervalAnalysis.cpp: [PR9590] Don't use ↵NAKAMURA Takumi2011-03-311-1/+3
| | | | | | | | | | std::pow(float,float) here. We don't expect the real "powf()" on some hosts (and powf() would be available on other hosts). For consistency, std::pow(double,double) may be called instead. Or, precision issue might attack us, to see unstable regalloc and stack coloring. llvm-svn: 128629
* Accept instructions that read undefined values.Jakob Stoklund Olesen2011-03-181-1/+9
| | | | | | | This is not supposed to happen, but I have seen the x86 rematter getting confused when rematerializing partial redefs. llvm-svn: 127857
* Dead code elimination may separate the live interval into multiple connected ↵Jakob Stoklund Olesen2011-03-171-1/+5
| | | | | | | | | components. I have convinced myself that it can only happen when a phi value dies. When it happens, allocate new virtual registers for the components. llvm-svn: 127827
* Clarify debugging output.Jakob Stoklund Olesen2011-03-161-2/+2
| | | | llvm-svn: 127771
* Make SpillIs an optional pointer. Avoid creating a bunch of temporary ↵Jakob Stoklund Olesen2011-03-101-8/+8
| | | | | | SmallVectors. llvm-svn: 127388
* Let shrinkToUses optionally return a list of now dead machine instructions.Jakob Stoklund Olesen2011-03-071-1/+6
| | | | llvm-svn: 127192
* Handle the special case of registers begin redefined by early-clobber defs.Jakob Stoklund Olesen2011-03-071-0/+7
| | | | | | | In this case, the value need to be available at the load index instead of the normal use index. llvm-svn: 127167
OpenPOWER on IntegriCloud