summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* - Each val# can have multiple kills.Evan Cheng2007-08-081-4/+5
| | | | | | | - Fix some minor bugs related to special markers on val# def. ~0U means undefined, ~1U means dead val#. llvm-svn: 40916
* - LiveInterval value#'s now have 3 components: def instruction #,Evan Cheng2007-08-071-7/+6
| | | | | | | | | | kill instruction #, and source register number (iff the value# is defined by a copy). - Now def instruction # is set for every value#, not just for copy defined ones. - Update some outdated code related inactive live ranges. - Kill info not yet set. That's next patch. llvm-svn: 40913
* If a livein is not used in the block. It's live through.Evan Cheng2007-06-271-5/+8
| | | | llvm-svn: 37764
* Fix an obvious bug. Old code only worked for the entry block.Evan Cheng2007-06-271-3/+4
| | | | llvm-svn: 37743
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-5/+4
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Add a target hook to allow loads from constant pools to be rematerialized, ↵Dan Gohman2007-06-141-2/+4
| | | | | | | | and an implementation for x86. llvm-svn: 37576
* Factor live variable analysis so it does not do register coalescingDavid Greene2007-06-081-1055/+3
| | | | | | | | | | simultaneously. Move that pass to SimpleRegisterCoalescing. This makes it easier to implement alternative register allocation and coalescing strategies while maintaining reuse of the existing live interval analysis. llvm-svn: 37520
* Only worry about intervening kill if there are more than one live ranges in ↵Evan Cheng2007-05-141-3/+5
| | | | | | the interval. llvm-svn: 37052
* Fix for PR1406:Evan Cheng2007-05-141-2/+35
| | | | | | | | | | | | | v1 = r2 = move v1 = op r2<kill> ... r2 = move v1 = op r2<kill> Clear the first r2 kill if v1 and r2 are joined. llvm-svn: 37050
* Drop 'const'Devang Patel2007-05-031-1/+1
| | | | llvm-svn: 36662
* Use 'static const char' instead of 'static const int'.Devang Patel2007-05-021-1/+1
| | | | | | | Due to darwin gcc bug, one version of darwin linker coalesces static const int, which defauts PassID based pass identification. llvm-svn: 36652
* Fix build error.Lauro Ramos Venancio2007-05-021-1/+1
| | | | llvm-svn: 36648
* Do not use typeinfo to identify pass in pass manager.Devang Patel2007-05-011-0/+1
| | | | llvm-svn: 36632
* Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.Evan Cheng2007-04-261-1/+1
| | | | llvm-svn: 36483
* Fix for PR1306.Evan Cheng2007-04-251-10/+48
| | | | | | | | | - A register def / use now implicitly affects sub-register liveness but does not affect liveness information of super-registers. - Def of a larger register (if followed by a use later) is treated as read/mod/write of a smaller register. llvm-svn: 36434
* VarInfo::UsedBlocks is no longer used. Remove.Evan Cheng2007-04-181-2/+1
| | | | llvm-svn: 36250
* Don't populate TryAgainList when coalescing only physical registers with ↵Evan Cheng2007-04-181-6/+6
| | | | | | virtual registers. llvm-svn: 36240
* Copy coalescing change to prevent a physical register from being pin to aEvan Cheng2007-04-171-77/+76
| | | | | | | | | | | | | long live interval that has low usage density. 1. Change order of coalescing to join physical registers with virtual registers first before virtual register intervals become too long. 2. Check size and usage density to determine if it's worthwhile to join. 3. If joining is aborted, assign virtual register live interval allocation preference field to the physical register. 4. Register allocator should try to allocate to the preferred register first (if available) to create identify moves that can be eliminated. llvm-svn: 36218
* Re-materialize all loads from fixed stack slots.Evan Cheng2007-04-041-5/+12
| | | | llvm-svn: 35660
* Trivially re-materializable instructions have spill weights that are half of ↵Evan Cheng2007-04-041-6/+6
| | | | | | what it would be otherwise. llvm-svn: 35658
* Ugh. Copy coalescer does not update register numbers.Evan Cheng2007-04-021-2/+15
| | | | llvm-svn: 35600
* Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep lengthEvan Cheng2007-03-301-5/+10
| | | | | | | | of dead def live interval at 1 to avoid multiple def's targeting the same register. The previous patch missed a case where the source operand is live-in. In that case, remove the whole interval. llvm-svn: 35512
* Move rematerialization out of beta.Evan Cheng2007-03-281-7/+1
| | | | llvm-svn: 35419
* Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing shouldEvan Cheng2007-03-281-3/+5
| | | | | | not violate that. llvm-svn: 35396
* Fix for PR1266. Don't mark a two address operand IsKill.Evan Cheng2007-03-261-3/+3
| | | | llvm-svn: 35365
* Fix for PR1257. Bug in live range shortening as a result of copy coalescingEvan Cheng2007-03-221-11/+9
| | | | | | where the destination is dead. llvm-svn: 35252
* First cut trivial re-materialization support.Evan Cheng2007-03-201-5/+26
| | | | llvm-svn: 35208
* Remove -reduce-joining-phys-regs options. Make it on by default.Evan Cheng2007-03-191-3/+1
| | | | llvm-svn: 35165
* Minor bug fix.Evan Cheng2007-03-191-1/+1
| | | | llvm-svn: 35153
* - Merge UsedBlocks info after two virtual registers are coalesced.Evan Cheng2007-03-181-23/+30
| | | | | | - Use distance to closest use to determine whether to abort coalescing. llvm-svn: 35141
* Joining a live interval of a physical register with a virtual one can turn outEvan Cheng2007-03-171-0/+54
| | | | | | | | | | | | to be really bad. Once they are joined they are not broken apart. Also, physical intervals cannot be spilled! Added a heuristic as a workaround for this. Be careful coalescing with a physical register if the virtual register uses are "far". Check if there are uses in the same loop as the source (copy instruction). Check if it is in the loop preheader, etc. llvm-svn: 35134
* Debugging output stuff.Evan Cheng2007-03-151-4/+4
| | | | llvm-svn: 35117
* Watch out for cases like this:Evan Cheng2007-03-031-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | entry (0x8b056f0, LLVM BB @0x8b01b30, ID#0): Live Ins: %r0 %r1 %r2 %r3 %reg1032 = tMOVrr %r3<kill> %reg1033 = tMOVri8 1 %reg1034 = tMOVri8 0 tCMPi8 %reg1029<kill>, 0 tBcc mbb<entry,0x8b06a10>, 0 Successors according to CFG: 0x8b06980 0x8b06a10 entry (0x8b06980, LLVM BB @0x8b01b30, ID#12): Predecessors according to CFG: 0x8b056f0 %reg1036 = tMOVrr %reg1034<kill> Successors according to CFG: 0x8b06a10 entry (0x8b06a10, LLVM BB @0x8b01b30, ID#13): Predecessors according to CFG: 0x8b056f0 0x8b06980 %reg1024<dead> = tMOVrr %reg1030<kill> ... reg1030 and r1 have already been joined. When reg1024 and reg1030 are joined, r1 live range from function entry to the tMOVrr instruction are dead. Eliminate r1 from the livein set of the entry BB, not the BB where the copy is. llvm-svn: 34866
* Dead live-in detection bug.Evan Cheng2007-03-021-2/+2
| | | | llvm-svn: 34843
* Oops.Evan Cheng2007-03-011-1/+0
| | | | llvm-svn: 34768
* Track all joined registers and eliminate unneeded kills after all joining ↵Evan Cheng2007-03-011-22/+42
| | | | | | are done. llvm-svn: 34767
* Joining an interval with a dead copy instruction. Shorten the live range to ↵Evan Cheng2007-02-261-20/+46
| | | | | | the last use. llvm-svn: 34645
* Fix a couple of bugs related IsDead back propagation during coalescing.Evan Cheng2007-02-251-5/+10
| | | | llvm-svn: 34595
* If the liveinterval of the source instruction has been extended, remove the ↵Evan Cheng2007-02-251-0/+6
| | | | | | IsKill marker. llvm-svn: 34594
* Handle cases when joining live intervals of two virtual registers.Evan Cheng2007-02-231-7/+17
| | | | llvm-svn: 34534
* Remove unnecessary isKill properties if a live range has been lengthened due ↵Evan Cheng2007-02-221-1/+24
| | | | | | to coalescing. llvm-svn: 34503
* Allow for live in registers for eh landing pads.Jim Laskey2007-02-211-5/+6
| | | | llvm-svn: 34475
* Out of bound reference.Evan Cheng2007-02-211-2/+2
| | | | llvm-svn: 34461
* Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.Evan Cheng2007-02-191-54/+135
| | | | llvm-svn: 34428
* For PR1207:Reid Spencer2007-02-191-134/+54
| | | | | | | Revert patches that caused the problem. Evan, please investigate and reapply when you've discovered the problem. llvm-svn: 34399
* - Changes how function livein's are handled, they now have a start index of 0.Evan Cheng2007-02-171-54/+134
| | | | | | | | - When coalescing a copy MI, if its destination is "dead", propagate the property to the source MI's destination if there are no intervening uses. - Detect dead function live-in's and remove them. llvm-svn: 34383
* Use BitVector instead of vector<bool> which can be extremely slow.Evan Cheng2007-02-151-1/+1
| | | | llvm-svn: 34302
* Allow any MachineBasicBlock (not just the entry block) to have live-in physicalEvan Cheng2007-02-131-39/+33
| | | | | | | registers. Make sure liveinterval analysis is correctly creating live ranges for them. llvm-svn: 34217
* Eliminate static ctors from StatisticsChris Lattner2006-12-191-15/+6
| | | | llvm-svn: 32698
* Changed llvm_ostream et all to OStream. llvm_cerr, llvm_cout, llvm_null, areBill Wendling2006-12-071-2/+2
| | | | | | now cerr, cout, and NullStream resp. llvm-svn: 32298
OpenPOWER on IntegriCloud