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path: root/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
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* Move some functionality for adding flags to MachineInstr's into methods on ↵Owen Anderson2008-01-241-1/+1
| | | | | | MachineInstr rather than LiveVariables. llvm-svn: 46295
* Only remat loads from immutable stack slots.Evan Cheng2008-01-101-2/+2
| | | | llvm-svn: 45831
* Simplify some code.Evan Cheng2008-01-101-8/+2
| | | | llvm-svn: 45830
* Don't use LiveVariables::VarInfo::DefInst.Owen Anderson2008-01-101-1/+8
| | | | llvm-svn: 45815
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-10/+10
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* simplify some code using new predicatesChris Lattner2008-01-071-3/+2
| | | | llvm-svn: 45689
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-7/+7
| | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
* Update CodeGen for MRegisterInfo --> TargetInstrInfo changes.Owen Anderson2008-01-071-3/+3
| | | | llvm-svn: 45673
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-5/+4
| | | | llvm-svn: 45667
* Don't recalculate the loop info and loop dominators analyses if they'reBill Wendling2008-01-041-0/+2
| | | | | | preserved. llvm-svn: 45596
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-10/+10
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* More cleanups for MachineOperand:Chris Lattner2007-12-301-1/+1
| | | | | | | | | | - Eliminate the static "print" method for operands, moving it into MachineOperand::print. - Change various set* methods for register flags to take a bool for the value to set it to. Remove unset* methods. - Group methods more logically by operand flavor in MachineOperand.h llvm-svn: 45461
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always ↵Evan Cheng2007-12-121-3/+15
| | | | | | re-materializable and they should not be spilled. llvm-svn: 44960
* Switch over to MachineLoopInfo.Evan Cheng2007-12-111-5/+5
| | | | llvm-svn: 44838
* Reverting 44702. It wasn't correct to rename them.Bill Wendling2007-12-081-1/+1
| | | | llvm-svn: 44727
* Renaming:Bill Wendling2007-12-081-1/+1
| | | | | | | isTriviallyReMaterializable -> hasNoSideEffects isReallyTriviallyReMaterializable -> isTriviallyReMaterializable llvm-svn: 44702
* Turning simple splitting on. Start testing new coalescer heuristics as new ↵Evan Cheng2007-12-061-1/+1
| | | | | | llcbeta. llvm-svn: 44660
* Fix for PR1831: if all defs of an interval are re-materializable, then it's ↵Evan Cheng2007-12-061-4/+34
| | | | | | a preferred spill candiate. llvm-svn: 44644
* MachineInstr can change. Store indexes instead.Evan Cheng2007-12-051-2/+12
| | | | llvm-svn: 44612
* If a split live interval is spilled again, remove the kill marker on its ↵Evan Cheng2007-12-051-1/+4
| | | | | | last use. llvm-svn: 44611
* Clobber more bugs.Evan Cheng2007-12-051-2/+3
| | | | llvm-svn: 44610
* Fix kill info for split intervals.Evan Cheng2007-12-051-10/+20
| | | | llvm-svn: 44609
* - Mark last use of a split interval as kill instead of letting spiller track it.Evan Cheng2007-12-051-26/+73
| | | | | | | | | This allows an important optimization to be re-enabled. - If all uses / defs of a split interval can be folded, give the interval a low spill weight so it would not be picked in case spilling is needed (avoid pushing other intervals in the same BB to be spilled). llvm-svn: 44601
* Discard split intervals made empty due to folding.Evan Cheng2007-12-041-5/+16
| | | | llvm-svn: 44565
* TypoEvan Cheng2007-12-031-1/+1
| | | | llvm-svn: 44532
* Update kill info for uses of split intervals.Evan Cheng2007-12-031-3/+2
| | | | llvm-svn: 44531
* Remove redundant foldMemoryOperand variants and other code clean up.Evan Cheng2007-12-021-70/+72
| | | | llvm-svn: 44517
* Fix a bug where splitting cause some unnecessary spilling.Evan Cheng2007-12-011-2/+12
| | | | llvm-svn: 44482
* Allow some reloads to be folded in multi-use cases. Specifically testl r, r ↵Evan Cheng2007-12-011-22/+32
| | | | | | -> cmpl [mem], 0. llvm-svn: 44479
* Do not fold reload into an instruction with multiple uses. It issues one ↵Evan Cheng2007-11-301-75/+86
| | | | | | extra load. llvm-svn: 44467
* Do not lose rematerialization info when spilling already split live intervals.Evan Cheng2007-11-291-14/+9
| | | | llvm-svn: 44443
* Fix a major performance issue with splitting. If there is a def (not def/use)Evan Cheng2007-11-291-60/+133
| | | | | | | | | | | | | | | in the middle of a split basic block, create a new live interval starting at the def. This avoid artifically extending the live interval over a number of cycles where it is dead. e.g. bb1: = vr1204 (use / kill) <= new interval starts and ends here. ... ... vr1204 = (new def) <= start a new interval here. = vr1204 (use) llvm-svn: 44436
* Replace the odd kill# hack with something less fragile.Evan Cheng2007-11-291-15/+10
| | | | llvm-svn: 44434
* Fixed various live interval splitting bugs / compile time issues.Evan Cheng2007-11-291-110/+200
| | | | llvm-svn: 44428
* Recover compile time regression.Evan Cheng2007-11-281-15/+25
| | | | llvm-svn: 44386
* Live interval splitting:Evan Cheng2007-11-171-61/+294
| | | | | | | | | | | | | | | | | | | When a live interval is being spilled, rather than creating short, non-spillable intervals for every def / use, split the interval at BB boundaries. That is, for every BB where the live interval is defined or used, create a new interval that covers all the defs and uses in the BB. This is designed to eliminate one common problem: multiple reloads of the same value in a single basic block. Note, it does *not* decrease the number of spills since no copies are inserted so the split intervals are *connected* through spill and reloads (or rematerialization). The newly created intervals can be spilled again, in that case, since it does not span multiple basic blocks, it's spilled in the usual manner. However, it can reuse the same stack slot as the previously split interval. This is currently controlled by -split-intervals-at-bb. llvm-svn: 44198
* Fix a thinko in post-allocation coalescer.Evan Cheng2007-11-151-3/+10
| | | | llvm-svn: 44166
* Clean up sub-register implementation by moving subReg information back toEvan Cheng2007-11-141-8/+2
| | | | | | | | | | | MachineOperand auxInfo. Previous clunky implementation uses an external map to track sub-register uses. That works because register allocator uses a new virtual register for each spilled use. With interval splitting (coming soon), we may have multiple uses of the same register some of which are of using different sub-registers from others. It's too fragile to constantly update the information. llvm-svn: 44104
* Refactor some code.Evan Cheng2007-11-121-292/+327
| | | | llvm-svn: 44010
* Simplify my (il)logic.Evan Cheng2007-11-071-11/+2
| | | | llvm-svn: 43819
* When the allocator rewrite a spill register with new virtual register, it ↵Evan Cheng2007-11-061-3/+12
| | | | | | | | replaces other operands of the same register. Watch out for situations where only some of the operands are sub-register uses. llvm-svn: 43776
* Fix a bug where a def use operand isn't being detected as a sub-register use.Evan Cheng2007-11-061-4/+7
| | | | llvm-svn: 43763
* Fix PR1187.Evan Cheng2007-11-051-1/+1
| | | | llvm-svn: 43692
* There are times when the coalescer would not coalesce away a copy but the copyEvan Cheng2007-11-031-0/+33
| | | | | | | | | | | | | | | | can be eliminated by the allocator is the destination and source targets the same register. The most common case is when the source and destination registers are in different class. For example, on x86 mov32to32_ targets GR32_ which contains a subset of the registers in GR32. The allocator can do 2 things: 1. Set the preferred allocation for the destination of a copy to that of its source. 2. After allocation is done, change the allocation of a copy destination (if legal) so the copy can be eliminated. This eliminates 443 extra moves from 403.gcc. llvm-svn: 43662
* Apply Chris' suggestions.Evan Cheng2007-10-171-1/+1
| | | | llvm-svn: 43069
* Clean up code that calculate MBB live-in's.Evan Cheng2007-10-171-0/+36
| | | | llvm-svn: 43060
* Did mean to leave this in. INSERT_SUBREG isn't being coalesced yet.Evan Cheng2007-10-121-2/+1
| | | | llvm-svn: 42916
* EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG likeEvan Cheng2007-10-121-173/+127
| | | | | | | | | (almost) a register copy. However, it always coalesced to the register of the RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub- register uses which adds subtle complications to load folding, spiller rewrite, etc. llvm-svn: 42899
* Kill cycle of an live range is always the last use index + 1.Evan Cheng2007-10-081-1/+1
| | | | llvm-svn: 42742
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