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* Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to ↵Evan Cheng2011-07-261-12/+12
| | | | | | createMCObjectStreamer. llvm-svn: 136031
* Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng2011-07-251-9/+9
| | | | | | createMCAsmBackend. llvm-svn: 136010
* Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.Evan Cheng2011-07-201-4/+3
| | | | | | | There is still a bit more refactoring left to do in Targets. But we are now very close to fixing all the layering issues in MC. llvm-svn: 135611
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-201-21/+2
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-201-1/+4
| | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! llvm-svn: 135569
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-191-1/+3
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-1/+2
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-141-1/+1
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-3/+11
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-10/+10
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* createMCInstPrinter doesn't need TargetMachine anymore.Evan Cheng2011-07-061-1/+1
| | | | llvm-svn: 134525
* Remove the ObjC ARC passes from the default optimization list, and addDan Gohman2011-07-051-4/+0
| | | | | | extension points to be used by clang. llvm-svn: 134444
* Move early tail duplication earlier.Rafael Espindola2011-07-041-6/+6
| | | | | | | | | | | | | | This fixes the issue noted in PR10251 where early tail dup of bbs with indirectbr would cause a bb to be duplicated into a loop preheader and then into its predecessors, creating phi nodes with identical operands just before register allocation. This helps with jsinterp.o size (__TEXT goes from 163568 to 126656) and a bit with performance 1.005x faster on sunspider (jits still enabled). The result on webkit with the jit disabled is more significant: 1.021x faster. llvm-svn: 134372
* Use the verbose asm flag instead of a new flag for decoding the LSDA.Bill Wendling2011-06-171-4/+1
| | | | llvm-svn: 133292
* Add an option that allows one to "decode" the LSDA.Bill Wendling2011-06-171-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LSDA is a bit difficult for the non-initiated to read. Even with comments, it's not always clear what's going on. This wraps the ASM streamer in a class that retains the LSDA and then emits a human-readable description of what's going on in it. So instead of having to make sense of: Lexception1: .byte 255 .byte 155 .byte 168 .space 1 .byte 3 .byte 26 Lset0 = Ltmp7-Leh_func_begin1 .long Lset0 Lset1 = Ltmp812-Ltmp7 .long Lset1 Lset2 = Ltmp913-Leh_func_begin1 .long Lset2 .byte 3 Lset3 = Ltmp812-Leh_func_begin1 .long Lset3 Lset4 = Leh_func_end1-Ltmp812 .long Lset4 .long 0 .byte 0 .byte 1 .byte 0 .byte 2 .byte 125 .long __ZTIi@GOTPCREL+4 .long __ZTIPKc@GOTPCREL+4 you can read this instead: ## Exception Handling Table: Lexception1 ## @LPStart Encoding: omit ## @TType Encoding: indirect pcrel sdata4 ## @TType Base: 40 bytes ## @CallSite Encoding: udata4 ## @Action Table Size: 26 bytes ## Action 1: ## A throw between Ltmp7 and Ltmp812 jumps to Ltmp913 on an exception. ## For type(s): __ZTIi@GOTPCREL+4 __ZTIPKc@GOTPCREL+4 ## Action 2: ## A throw between Ltmp812 and Leh_func_end1 does not have a landing pad. llvm-svn: 133286
* The ARC language-specific optimizer. Credit to Dan Gohman.John McCall2011-06-151-0/+4
| | | | llvm-svn: 133108
* Stub out support for Win64-style exceptions. Note that this is merely usingCharles Davis2011-05-271-0/+1
| | | | | | | the Win64 EH mechanism to implement GCC-style exceptions. LLVM supports hardly anything else at this point! llvm-svn: 132234
* eliminate dependence on StandardPasses.h. The code generator's pass pipelineChris Lattner2011-05-221-2/+6
| | | | | | should eventually convert to PMBuilder, but I don't plan to do this. llvm-svn: 131819
* Remove the DwarfTable enum.Rafael Espindola2011-05-051-1/+0
| | | | llvm-svn: 130959
* Add all the plumbing needed for MC to expand cfi to the old tables inRafael Espindola2011-04-301-0/+1
| | | | | | | the final assembly. It is the same technique used when targeting assemblers that don't support .loc. llvm-svn: 130587
* Integrated-As: Add support for setting the AllowTemporaryLabels flag viaDaniel Dunbar2011-03-281-0/+6
| | | | | | integrated-as. llvm-svn: 128431
* We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling2011-03-211-1/+1
| | | | | | | | | the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
* Beginnings of MC-JIT code generation.Jim Grosbach2011-03-181-0/+26
| | | | | | | | | | | Proof-of-concept code that code-gens a module to an in-memory MachO object. This will be hooked up to a run-time dynamic linker library (see: llvm-rtdyld for similarly conceptual work for that part) which will take the compiled object and link it together with the rest of the system, providing back to the JIT a table of available symbols which will be used to respond to the getPointerTo*() queries. llvm-svn: 127916
* Some first rudimentary support for ARM EHABI: print exception table in "text ↵Anton Korobeynikov2011-03-051-0/+1
| | | | | | mode". llvm-svn: 127099
* Delete the GEPSplitter experiment.Dan Gohman2011-02-281-12/+0
| | | | llvm-svn: 126671
* Add support for the --noexecstack option.Rafael Espindola2011-01-231-1/+2
| | | | llvm-svn: 124077
* Add a possibility to switch between CFI directives- and table-based frame ↵Anton Korobeynikov2011-01-141-1/+2
| | | | | | description emission. Currently all the backends use table-based stuff. llvm-svn: 123476
* Pass a Banner argument to the machine code verifier both fromJakob Stoklund Olesen2010-12-181-1/+1
| | | | | | | | createMachineVerifierPass and MachineFunction::verify. The banner is printed before the machine code dump, just like the printer pass. llvm-svn: 122113
* MC: Make TargetAsmBackend available to the AsmStreamer.Daniel Dunbar2010-12-161-2/+5
| | | | | | - Treaty talks on the non-proliferation of MC objects broke down. llvm-svn: 121949
* Fixed version of 121434 with no new memory leaks.Rafael Espindola2010-12-101-22/+9
| | | | llvm-svn: 121471
* Revert my previous patch to make the valgrind bots happy.Rafael Espindola2010-12-101-9/+22
| | | | llvm-svn: 121461
* Initial support for the cfi directives. This is just enough to getRafael Espindola2010-12-091-22/+9
| | | | | | | | | | | f: .cfi_startproc nop .cfi_endproc assembled (on ELF). llvm-svn: 121434
* Change some methods in MCDwarf.cpp to be able to handle an arbitraryRafael Espindola2010-11-191-5/+23
| | | | | | | | | | | | MCStreamer instead of just MCObjectStreamer. Address changes cannot be as efficient as we have to use DW_LNE_set_addres, but at least most of the logic is shared. This will be used so that, with CodeGen still using EmitDwarfLocDirective, llvm-gcc is able to produce debug_line sections without needing an assembler that supports .loc. llvm-svn: 119777
* Oops, missed this file when remaing ExpandPseudos to ExpandISelPseudos.Dan Gohman2010-11-181-2/+2
| | | | llvm-svn: 119717
* Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng2010-11-171-1/+3
| | | | | | | | | | | | | | | | | | | | | and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
* Split pseudo-instruction expansion into a separate pass, to make itDan Gohman2010-11-161-0/+3
| | | | | | | easier to debug, and to avoid complications when the CFG changes in the middle of the instruction selection process. llvm-svn: 119382
* Add registry hook for assembly text outputChe-Liang Chiou2010-11-081-4/+5
| | | | llvm-svn: 118394
* Add TypeBasedAliasAnalysis to the standard pass lists. Note that itDan Gohman2010-10-181-2/+2
| | | | | | is currently inert by default. llvm-svn: 116732
* Make BasicAliasAnalysis a normal AliasAnalysis implementation whichDan Gohman2010-10-181-0/+4
| | | | | | | | | | | | does normal initialization and normal chaining. Change the default AliasAnalysis implementation to NoAlias. Update StandardCompileOpts.h and friends to explicitly request BasicAliasAnalysis. Update tests to explicitly request -basicaa. llvm-svn: 116720
* Call InitSections in llc and clang so that the binaries produced by themRafael Espindola2010-10-081-0/+1
| | | | | | are easier to diff with those produced by llvm-mc. llvm-svn: 116095
* Stop using the dom frontier in DwarfEHPrepare by not promoting alloca'sDuncan Sands2010-08-311-1/+1
| | | | | | | | any more. I plan to reimplement alloca promotion using SSAUpdater later. It looks like Bill's URoR logic really always needs domtree, so the pass now always asks for domtree info. llvm-svn: 112597
* Move enabling the local stack allocation pass into the target where it belongs.Jim Grosbach2010-08-241-15/+3
| | | | | | | For now it's still a command line option, but the interface to the generic code doesn't need to know that. llvm-svn: 111942
* Add a local stack object block allocation pass. This is still anJim Grosbach2010-08-141-0/+16
| | | | | | | | | | | | | | | | | | experimental pass that allocates locals relative to one another before register allocation and then assigns them to actual stack slots as a block later in PEI. This will eventually allow targets with limited index offset range to allocate additional base registers (not just FP and SP) to more efficiently reference locals, as well as handle situations where locals cannot be referenced via SP or FP at all (dynamic stack realignment together with variable sized objects, for example). It's currently incomplete and almost certainly buggy. Work in progress. Disabled by default and gated via the -enable-local-stack-alloc command line option. rdar://8277890 llvm-svn: 111059
* tidy up whitespace a bitJim Grosbach2010-08-131-7/+6
| | | | llvm-svn: 111019
* Merge the OptimizeExts and OptimizeCmps passes into one PeepholeOptimizerBill Wendling2010-08-091-2/+1
| | | | | | | pass. This pass should expand with all of the small, fine-grained optimization passes to reduce compile time and increase happiment. llvm-svn: 110627
* Add the Optimize Compares pass (disabled by default).Bill Wendling2010-08-061-0/+1
| | | | | | | | | | | | | | | | This pass tries to remove comparison instructions when possible. For instance, if you have this code: sub r1, 1 cmp r1, 0 bz L1 and "sub" either sets the same flag as the "cmp" instruction or could be converted to set the same flag, then we can eliminate the "cmp" instruction all together. This is a important for ARM where the ALU instructions could set the CPSR flag, but need a special suffix ('s') to do so. llvm-svn: 110423
* Remove double-def checking from MachineVerifier, so a register does not have toJakob Stoklund Olesen2010-08-051-13/+7
| | | | | | | | | | be killed before being redefined. These checks are usually disabled, and usually fail when enabled. We de facto allow live registers to be redefined without a kill, the corresponding assertions in RegScavenger were removed long ago. llvm-svn: 110362
* The lower invoke pass needs to have unreachable code elimination run after itBill Wendling2010-08-041-2/+4
| | | | | | because it could create such things. This fixes a MingW buildbot test failure. llvm-svn: 110279
* The EH prepare passes really want to be the last passes run before code-gen.Bill Wendling2010-08-041-5/+5
| | | | llvm-svn: 110248
* Plug the remaining MC leaks by giving MCObjectStreamer/MCAsmStreamer ↵Benjamin Kramer2010-07-291-4/+0
| | | | | | ownership of the TargetAsmBackend and the MCCodeEmitter. llvm-svn: 109767
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