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* Added TargetPassConfig::setOptAndrew Trick2012-02-081-0/+2
| | | | llvm-svn: 150093
* Add TargetPassConfig to the PassManager for use inside passesAndrew Trick2012-02-061-2/+2
| | | | llvm-svn: 149926
* Fix a leak!Nick Lewycky2012-02-041-0/+2
| | | | | | | | | | | | Andy, in a previous commit you made this into an ImmutablePass so that you could add it to the PassManager, then in the next commit you left it a Pass but removed the code that added it to the PM. If you do add it to the PM then the PM should take care of deleting it, but it's also true that nothing in codegen needs this object to exist after it's done its work here. It's not clear to me which design you want; this should likely either cease to be a Pass or be added to the PM where other parts of CodeGen will request it. llvm-svn: 149765
* TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2012-02-041-13/+92
| | | | | | | | | | Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. llvm-svn: 149754
* Move TargetPassConfig implementation into Passes.cppAndrew Trick2012-02-041-304/+2
| | | | llvm-svn: 149753
* Make TargetPassConfig an ImmutablePass so CodeGenPasses can query optionsAndrew Trick2012-02-041-15/+2
| | | | llvm-svn: 149752
* Initialize all common codegen passes before configuration so we can use ↵Andrew Trick2012-02-031-0/+7
| | | | | | their PassIDs. llvm-svn: 149705
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-031-44/+50
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. llvm-svn: 149672
* Add an option to disable buggy copy propagation passAnton Korobeynikov2012-01-221-1/+3
| | | | llvm-svn: 148662
* 80-col violationAndrew Trick2012-01-131-3/+3
| | | | llvm-svn: 148102
* Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth2012-01-101-0/+1
| | | | | | | | of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-101-2/+0
| | | | llvm-svn: 147855
* Remove the logging streamer.Rafael Espindola2012-01-101-5/+0
| | | | llvm-svn: 147820
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-071-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-11/+9
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-161-30/+28
| | | | | | | and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. llvm-svn: 144788
* Begin collecting some of the statistics for block placement discussed onChandler Carruth2011-11-021-0/+8
| | | | | | | | | | | | | the mailing list. Suggestions for other statistics to collect would be awesome. =] Currently these are implemented as a separate pass guarded by a separate flag. I'm not thrilled by that, but I wanted to be able to collect the statistics for the old code placement as well as the new in order to have a point of comparison. I'm planning on folding them into the single pass if / when there is only one pass of interest. llvm-svn: 143537
* Make assert() message more informative.Jim Grosbach2011-10-251-1/+2
| | | | | | PR11217. llvm-svn: 142956
* Implement a block placement pass based on the branch probability andChandler Carruth2011-10-211-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | block frequency analyses. This differs substantially from the existing block-placement pass in LLVM: 1) It operates on the Machine-IR in the CodeGen layer. This exposes much more (and more precise) information and opportunities. Also, the results are more stable due to fewer transforms ocurring after the pass runs. 2) It uses the generalized probability and frequency analyses. These can model static heuristics, code annotation derived heuristics as well as eventual profile loading. By basing the optimization on the analysis interface it can work from any (or a combination) of these inputs. 3) It uses a more aggressive algorithm, both building chains from tho bottom up to maximize benefit, and using an SCC-based walk to layout chains of blocks in a profitable ordering without O(N^2) iterations which the old pass involves. The pass is currently gated behind a flag, and not enabled by default because it still needs to grow some important features. Most notably, it needs to support loop aligning and careful layout of loop structures much as done by hand currently in CodePlacementOpt. Once it supports these, and has sufficient testing and quality tuning, it should replace both of these passes. Thanks to Nick Lewycky and Richard Smith for help authoring & debugging this, and to Jakob, Andy, Eric, Jim, and probably a few others I'm forgetting for reviewing and answering all my questions. Writing a backend pass is *sooo* much better now than it used to be. =D llvm-svn: 142641
* Add support for a new extension to the .file directive:Nick Lewycky2011-10-171-0/+1
| | | | | | | | | | .file filenumber "directory" "filename" This removes one join+split of the directory+filename in MC internals. Because bitcode files have independent fields for directory and filenames in debug info, this patch may change the .o files written by existing .bc files. llvm-svn: 142300
* Comment grammar fixes.Torok Edwin2011-09-301-5/+6
| | | | | | thanks to Duncan. llvm-svn: 140850
* Instead of crashing when MCAsmInfo is NULL, add an assert.Torok Edwin2011-09-301-0/+5
| | | | | | | This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location, and if you include the old one by accident you will trigger this assert. llvm-svn: 140848
* Don't conditionalize execution of the SjLj EH prepare pass.Bill Wendling2011-09-281-5/+1
| | | | | | | We may need an SjLj EH preparation pass for some call site information, at least in the short term. llvm-svn: 140674
* This is the start of the new SjLj EH preparation pass, which will replace theBill Wendling2011-09-271-1/+5
| | | | | | | | | | | | | | | | | | | current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. llvm-svn: 140646
* Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.Jakob Stoklund Olesen2011-09-251-2/+2
| | | | | | No functional change intended. llvm-svn: 140470
* Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ↵James Molloy2011-09-071-2/+2
| | | | | | handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Add llc flags to disable machine DCE and CSE.Jakob Stoklund Olesen2011-08-191-2/+8
| | | | | | This is useful for unit tests. llvm-svn: 138028
* Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to ↵Evan Cheng2011-07-261-12/+12
| | | | | | createMCObjectStreamer. llvm-svn: 136031
* Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng2011-07-251-9/+9
| | | | | | createMCAsmBackend. llvm-svn: 136010
* Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.Evan Cheng2011-07-201-4/+3
| | | | | | | There is still a bit more refactoring left to do in Targets. But we are now very close to fixing all the layering issues in MC. llvm-svn: 135611
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-201-21/+2
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-201-1/+4
| | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! llvm-svn: 135569
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-191-1/+3
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-1/+2
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-141-1/+1
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-3/+11
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-10/+10
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* createMCInstPrinter doesn't need TargetMachine anymore.Evan Cheng2011-07-061-1/+1
| | | | llvm-svn: 134525
* Remove the ObjC ARC passes from the default optimization list, and addDan Gohman2011-07-051-4/+0
| | | | | | extension points to be used by clang. llvm-svn: 134444
* Move early tail duplication earlier.Rafael Espindola2011-07-041-6/+6
| | | | | | | | | | | | | | This fixes the issue noted in PR10251 where early tail dup of bbs with indirectbr would cause a bb to be duplicated into a loop preheader and then into its predecessors, creating phi nodes with identical operands just before register allocation. This helps with jsinterp.o size (__TEXT goes from 163568 to 126656) and a bit with performance 1.005x faster on sunspider (jits still enabled). The result on webkit with the jit disabled is more significant: 1.021x faster. llvm-svn: 134372
* Use the verbose asm flag instead of a new flag for decoding the LSDA.Bill Wendling2011-06-171-4/+1
| | | | llvm-svn: 133292
* Add an option that allows one to "decode" the LSDA.Bill Wendling2011-06-171-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LSDA is a bit difficult for the non-initiated to read. Even with comments, it's not always clear what's going on. This wraps the ASM streamer in a class that retains the LSDA and then emits a human-readable description of what's going on in it. So instead of having to make sense of: Lexception1: .byte 255 .byte 155 .byte 168 .space 1 .byte 3 .byte 26 Lset0 = Ltmp7-Leh_func_begin1 .long Lset0 Lset1 = Ltmp812-Ltmp7 .long Lset1 Lset2 = Ltmp913-Leh_func_begin1 .long Lset2 .byte 3 Lset3 = Ltmp812-Leh_func_begin1 .long Lset3 Lset4 = Leh_func_end1-Ltmp812 .long Lset4 .long 0 .byte 0 .byte 1 .byte 0 .byte 2 .byte 125 .long __ZTIi@GOTPCREL+4 .long __ZTIPKc@GOTPCREL+4 you can read this instead: ## Exception Handling Table: Lexception1 ## @LPStart Encoding: omit ## @TType Encoding: indirect pcrel sdata4 ## @TType Base: 40 bytes ## @CallSite Encoding: udata4 ## @Action Table Size: 26 bytes ## Action 1: ## A throw between Ltmp7 and Ltmp812 jumps to Ltmp913 on an exception. ## For type(s): __ZTIi@GOTPCREL+4 __ZTIPKc@GOTPCREL+4 ## Action 2: ## A throw between Ltmp812 and Leh_func_end1 does not have a landing pad. llvm-svn: 133286
* The ARC language-specific optimizer. Credit to Dan Gohman.John McCall2011-06-151-0/+4
| | | | llvm-svn: 133108
* Stub out support for Win64-style exceptions. Note that this is merely usingCharles Davis2011-05-271-0/+1
| | | | | | | the Win64 EH mechanism to implement GCC-style exceptions. LLVM supports hardly anything else at this point! llvm-svn: 132234
* eliminate dependence on StandardPasses.h. The code generator's pass pipelineChris Lattner2011-05-221-2/+6
| | | | | | should eventually convert to PMBuilder, but I don't plan to do this. llvm-svn: 131819
* Remove the DwarfTable enum.Rafael Espindola2011-05-051-1/+0
| | | | llvm-svn: 130959
* Add all the plumbing needed for MC to expand cfi to the old tables inRafael Espindola2011-04-301-0/+1
| | | | | | | the final assembly. It is the same technique used when targeting assemblers that don't support .loc. llvm-svn: 130587
* Integrated-As: Add support for setting the AllowTemporaryLabels flag viaDaniel Dunbar2011-03-281-0/+6
| | | | | | integrated-as. llvm-svn: 128431
* We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling2011-03-211-1/+1
| | | | | | | | | the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
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