bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[ARM, AArch64] Match additional patterns to ldN instructions	Matthew Simpson	2016-05-19	1	-5/+107
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	When matching an interleaved load to an ldN pattern, the interleaved access pass checks that all users of the load are shuffles. If the load is used by an instruction other than a shuffle, the pass gives up and an ldN is not generated. This patch considers users of the load that are extractelement instructions. It attempts to modify the extracts to use one of the available shuffles rather than the load. After the transformation, the load is only used by shuffles and will then be matched with an ldN pattern. Differential Revision: http://reviews.llvm.org/D20250 llvm-svn: 270142
*	[ARM, AArch64] Properly initialize InterleavedAccessPass	Matthew Simpson	2016-05-19	1	-4/+0
\| \| \| \| \| \| \|	InterleavedAccessPass is an IR-level pass, so this change will enable testing it with opt. This is part of D20250. llvm-svn: 270101
*	Cleanup comments. NFC.	Chad Rosier	2016-05-02	1	-7/+9
\| \| \| \|	llvm-svn: 268233
*	[ARM][AArch64] Turn on by default interleaved access lowering	Silviu Baranga	2015-09-01	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Summary: Interleaved access lowering removes a memory operation and a sequence of vector shuffles and replaces it with a series of memory operations. This should be always beneficial. This pass in only enabled on ARM/AArch64. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D12145 llvm-svn: 246540
*	Rename inst_range() to instructions() for consistency. NFC	Nico Rieck	2015-08-06	1	-1/+1
\| \| \| \|	llvm-svn: 244248
*	[InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on ↵	Hao Liu	2015-06-26	1	-0/+1
\| \| \| \| \| \|	windows. llvm-svn: 240760
*	[InterleavedAccess] Add a pass InterleavedAccess to identify interleaved ↵	Hao Liu	2015-06-26	1	-0/+285
	memory accesses and transform into target specific intrinsics. E.g. An interleaved load (Factor = 2): %wide.vec = load <8 x i32>, <8 x i32>* %ptr %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6> %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7> It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend. E.g. An interleaved store (Factor = 3): %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> %i.vec, <12 x i32>* %ptr It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend. Differential Revision: http://reviews.llvm.org/D10533 llvm-svn: 240751