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* Refactor UpdatePredRedefs and StepForward to avoid duplication. NFCPete Cooper2015-05-051-21/+14
| | | | | | | | | | Note, this is a reapplication of r236515 with a fix to not assert on non-register operands, but instead only handle them until the subsequent commit. Original commit message follows. The code was basically the same here already. Just added an out parameter for a vector of seen defs so that UpdatePredRedefs can call StepForward first, then do its own post processing on the seen defs. Will be used in the next commit to also handle regmasks. llvm-svn: 236538
* Revert "Refactor UpdatePredRedefs and StepForward to avoid duplication. NFC"Pete Cooper2015-05-051-14/+21
| | | | | | | | This reverts commit 963cdbccf6e5578822836fd9b2ebece0ba9a60b7 (ie r236514) This is to get the bots green while i investigate. llvm-svn: 236518
* Revert "Fix IfConverter to handle regmask machine operands."Pete Cooper2015-05-051-14/+0
| | | | | | | | This reverts commit b27413cbfd78d959c18e713bfa271fb69e6b3303 (ie r236515). This is to get the bots green while i investigate the failures. llvm-svn: 236517
* Fix IfConverter to handle regmask machine operands.Pete Cooper2015-05-051-0/+14
| | | | | | | | | | A regmask (typically seen on a call) clobbers the set of registers it lists. The IfConverter, in UpdatePredRedefs, was handling register defs, but not regmasks. These are slightly different to a def in that we need to add both an implicit use and def to appease the machine verifier. Otherwise, uses after the if converted call could think they are reading an undefined register. Reviewed by Matthias Braun and Quentin Colombet. llvm-svn: 236515
* Refactor UpdatePredRedefs and StepForward to avoid duplication. NFCPete Cooper2015-05-051-21/+14
| | | | | | | | The code was basically the same here already. Just added an out parameter for a vector of seen defs so that UpdatePredRedefs can call StepForward first, then do its own post processing on the seen defs. Will be used in the next commit to also handle regmasks. llvm-svn: 236514
* [CodeGen][IfCvt] Don't re-ifcvt blocks with unanalyzable terminators.Ahmed Bougacha2015-03-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we couldn't analyze its terminator (i.e., it's an indirectbr, or some other weirdness), we can't safely re-if-convert a predicated block, because we can't tell whether the predicated terminator can fallthrough (it does). Currently, we would completely ignore the fallthrough successor. In the added testcase, this means we used to generate: ... @ %entry: cmp r5, #21 ittt ne @ %cc1f: cmpne r7, #42 @ %cc2t: strne.w r5, [r8] movne pc, r10 @ %cc1t: ... Whereas the successor of %cc1f was originally %bb1. With the fix, we get the correct: ... @ %entry: cmp r5, #21 itt eq @ %cc1t: streq.w r5, [r11] moveq pc, r0 @ %cc1f: cmp r7, #42 itt ne @ %cc2t: strne.w r5, [r8] movne pc, r10 @ %bb1: ... rdar://20192768 Differential Revision: http://reviews.llvm.org/D8509 llvm-svn: 232872
* Simplify expressions involving boolean constants with clang-tidyDavid Blaikie2015-03-091-1/+1
| | | | | | | | Patch by Richard (legalize at xmission dot com). Differential Revision: http://reviews.llvm.org/D8154 llvm-svn: 231617
* Replace std::copy with a back inserter with vector append where feasibleBenjamin Kramer2015-02-281-6/+4
| | | | | | | | | All of the cases were just appending from random access iterators to a vector. Using insert/append can grow the vector to the perfect size directly and moves the growing out of the loop. No intended functionalty change. llvm-svn: 230845
* The subtarget is cached on the MachineFunction. Access it directly.Eric Christopher2015-01-271-7/+5
| | | | llvm-svn: 227173
* Remove unnecessary TargetMachine.h includes.Eric Christopher2014-10-141-1/+0
| | | | llvm-svn: 219672
* Change MCSchedModel to be a struct of statically initialized data.Pete Cooper2014-09-021-1/+1
| | | | | | | | This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour Reviewed by Andy Trick and Chandler C llvm-svn: 216919
* CodeGen: switch to a range based for loopSaleem Abdulrasool2014-08-091-3/+4
| | | | | | Use a range based for loop instead of manual iteration. NFC. llvm-svn: 215287
* [Branch probability] Recompute branch weights of tail-merged basic blocks.Akira Hatanaka2014-08-071-2/+6
| | | | | | | | | | | | | | | BranchFolderPass was not correctly setting the basic block branch weights when tail-merging created or merged blocks. This patch recomutes the weights of tail-merged blocks using the following formula: branch_weight(merged block to successor j) = sum(block_frequency(bb) * branch_probability(bb -> j)) bb is a block that is in the set of merged blocks. <rdar://problem/16256423> llvm-svn: 215135
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-8/+6
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-7/+7
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | | | | | | define below all header includes in the lib/CodeGen/... tree. While the current modules implementation doesn't check for this kind of ODR violation yet, it is likely to grow support for it in the future. It also removes one layer of macro pollution across all the included headers. Other sub-trees will follow. llvm-svn: 206837
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-20/+21
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-071-2/+2
| | | | | | class. llvm-svn: 203220
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-1/+1
| | | | | | Remove the old functions. llvm-svn: 202636
* PGO branch weight: fix PR18752.Manman Ren2014-02-071-5/+4
| | | | | | | Fix a bug triggered in IfConverterTriangle when CvtBB has multiple predecessors by getting the weights before removing a successor. llvm-svn: 200958
* PGO branch weight: update edge weights in IfConverter.Manman Ren2014-01-291-0/+47
| | | | | | | | | | | | | This commit only handles IfConvertTriangle. To update edge weights of a successor, one interface is added to MachineBasicBlock: /// Set successor weight of a given iterator. setSuccWeight(succ_iterator I, uint32_t weight) An existing testing case test/CodeGen/Thumb2/v8_IT_5.ll is updated, since we now correctly update the edge weights, the cold block is placed at the end of the function and we jump to the cold block. llvm-svn: 200428
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-1/+1
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* Convert register liveness tracking to work on a sub-register level instead ↵Juergen Ributzka2013-12-141-24/+22
| | | | | | | | of just register units. Reviewed by Andy llvm-svn: 197315
* Revert "Convert liveness tracking to work on a sub-register level instead of ↵Andrew Trick2013-12-131-22/+24
| | | | | | | | | | just register units." This reverts commit r197253. This was a great change, but Juergen should be the commit author. llvm-svn: 197262
* Convert liveness tracking to work on a sub-register level instead of just ↵Andrew Trick2013-12-131-24/+22
| | | | | | register units. llvm-svn: 197253
* LiveRegUnits: Use *MBB for consistency and convenience.Andrew Trick2013-10-141-6/+6
| | | | llvm-svn: 192634
* Use a SparseSet in LiveRegUnits.Andrew Trick2013-10-141-19/+18
| | | | | | | | | | Some clients may add block live ins and may track liveness over a large scope. This guarantees an efficient implementation in all cases with no memory allocation/deallocation, independent of the number of target registers. It could be slightly less convenient but is fine in the expected case. llvm-svn: 192622
* Convert LiveRegUnits methods to the current convention (it's new code).Andrew Trick2013-10-141-12/+12
| | | | llvm-svn: 192619
* fConversion: Attempt #2 at fixing the MSVC build.Benjamin Kramer2013-10-111-2/+2
| | | | llvm-svn: 192492
* IfConversion: Try to unbreak the MSVC build.Benjamin Kramer2013-10-111-1/+1
| | | | llvm-svn: 192487
* Remove kill flags after if conversion if necessaryMatthias Braun2013-10-111-66/+89
| | | | | | | | | | | | | | | | | | | When if converting something like: true: ... = R0<kill> false: ... = R0<kill> then the instructions of the true block must not have a <kill> flag anymore, as the instruction of the false block follow and do still read the R0 value. Specifically this patch determines the set of register live-in in the false block (possibly after simulating the liveness changes of the duplicated instructions). Each of these live-in registers mustn't be killed. llvm-svn: 192482
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-091-21/+18
| | | | | | | | | IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
* Fix a bug in IfConverter with nested predicates.Quentin Colombet2013-07-241-3/+3
| | | | | | | | | | | | | | | | | | | Prior to this patch, IfConverter may widen the cases where a sequence of instructions were executed because of the way it uses nested predicates. This result in incorrect execution. For instance, Let A be a basic block that flows conditionally into B and B be a predicated block. B can be predicated with A.BrToBPredicate into A iff B.Predicate is less "permissive" than A.BrToBPredicate, i.e., iff A.BrToBPredicate subsumes B.Predicate. The IfConverter was checking the opposite: B.Predicate subsumes A.BrToBPredicate. <rdar://problem/14379453> llvm-svn: 187071
* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-221-8/+8
| | | | llvm-svn: 182531
* Teach if-converter to avoid removing BBs whose addresses are takne. ↵Evan Cheng2013-05-051-2/+19
| | | | | | rdar://13782395 llvm-svn: 181160
* Manually remove successors in if conversion when CopyAndPredicateBlock is usedHal Finkel2013-04-101-0/+8
| | | | | | | | | | | | | | | In the simple and triangle if-conversion cases, when CopyAndPredicateBlock is used because the to-be-predicated block has other predecessors, we need to explicitly remove the old copied block from the successors list. Normally if conversion relies on TII->AnalyzeBranch combined with BB->CorrectExtraCFGEdges to cleanup the successors list, but if the predicated block contained an un-analyzable branch (such as a now-predicated return), then this will fail. These extra successors were causing a problem on PPC because it was causing later passes (such as PPCEarlyReturm) to leave dead return-only basic blocks in the code. llvm-svn: 179227
* Avoid creating duplicate CFG edges in the IfConversion pass.Jakob Stoklund Olesen2013-01-241-1/+1
| | | | | | Patch by Stefan Hepp. llvm-svn: 173395
* Split TargetLowering into a CodeGen and a SelectionDAG part.Benjamin Kramer2013-01-111-1/+1
| | | | | | | | | This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still a complete mess but as long as the edges consist of virtual call it doesn't cause breakage. BasicTTI did static calls and thus broke some build configurations. llvm-svn: 172246
* Use MachineInstrBuilder in a few CodeGen passes.Jakob Stoklund Olesen2012-12-201-3/+3
| | | | | | This automatically passes a context pointer to MI->addOperand(). llvm-svn: 170711
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-9/+9
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Reduce duplicated hash map lookups.Benjamin Kramer2012-08-221-2/+1
| | | | llvm-svn: 162362
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-2/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Start implementing pre-ra if-converter: using speculation and selects to ↵Evan Cheng2012-06-081-6/+15
| | | | | | eliminate branches. llvm-svn: 158234
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-11/+10
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* If-converter models predicated defs as read + write. The read should be ↵Evan Cheng2012-05-301-1/+2
| | | | | | marked as 'undef' since it may not already be live. This appeases -verify-machineinstrs. llvm-svn: 157662
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-5/+5
| | | | | | static data size. llvm-svn: 152016
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-081-3/+2
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-6/+5
| | | | llvm-svn: 149816
* Add a if-conversion optimization that allows 'true' side of a diamond to beEvan Cheng2011-12-191-5/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unpredicated. That is, turn subeq r0, r1, #1 addne r0, r1, #1 into sub r0, r1, #1 addne r0, r1, #1 For targets where conditional instructions are always executed, this may be beneficial. It may remove pseudo anti-dependency in out-of-order execution CPUs. e.g. op r1, ... str r1, [r10] ; end-of-life of r1 as div result cmp r0, #65 movne r1, #44 ; raw dependency on previous r1 moveq r1, #12 If movne is unpredicated, then op r1, ... str r1, [r10] cmp r0, #65 mov r1, #44 ; r1 written unconditionally moveq r1, #12 Both mov and moveq are no longer depdendent on the first instruction. This gives the out-of-order execution engine more freedom to reorder them. This has passed entire LLVM test suite. But it has not been enabled for any ARM variant pending more performance evaluation. rdar://8951196 llvm-svn: 146914
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