summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/GlobalISel
Commit message (Collapse)AuthorAgeFilesLines
...
* GlobalISel: Support narrowScalar for uneven loadsMatt Arsenault2019-01-301-11/+40
| | | | llvm-svn: 352594
* GlobalISel: Handle some odd splits in fewerElementsVectorMatt Arsenault2019-01-301-10/+55
| | | | | | Also add some quick hacks to AMDGPU legality for the tests. llvm-svn: 352591
* GlobalISel: Handle more cases for widenScalar for G_STOREMatt Arsenault2019-01-301-3/+10
| | | | llvm-svn: 352585
* GlobalISel: Fix unused variable warning in release buildsMatt Arsenault2019-01-291-2/+1
| | | | llvm-svn: 352565
* GlobalISel: Partially implement widenScalar for MERGE_VALUESMatt Arsenault2019-01-291-0/+40
| | | | llvm-svn: 352560
* GlobalISel: Fix narrowScalar for load/store with different mem sizeMatt Arsenault2019-01-291-2/+27
| | | | | | | | | | This was ignoring the memory size, and producing multiple loads/stores if the operand size was different from the memory size. I assume this is the intent of not having an explicit G_ANYEXTLOAD (although I think that would probably be better). llvm-svn: 352523
* [GlobalISel][AArch64] Add legalization for G_FLOGJessica Paquette2019-01-281-1/+7
| | | | | | | | | | This adds support for legalizing G_FLOG into a RTLib call. It adds a legalizer test, and updates the existing floating point tests. https://reviews.llvm.org/D57347 llvm-svn: 352429
* [GlobalISel][AArch64] Add instruction selection support for @llvm.log10Jessica Paquette2019-01-281-1/+7
| | | | | | | | | | This adds instruction selection support for @llvm.log10 in AArch64. It teaches GISel to lower it to a library call, updates the relevant tests, and adds a legalizer test for log10. https://reviews.llvm.org/D57341 llvm-svn: 352418
* [GlobalISel] Add ISel support for @llvm.lifetime.start and @llvm.lifetime.endJessica Paquette2019-01-281-6/+27
| | | | | | | | | | | | | | | | | | This adds ISel support for lifetime markers in opt levels above O0. It also updates the arm64-irtranslator test, and updates some AArch64 tests that use them for added coverage. It also adds a testcase taken from the X86 codegen tests which verified a bug caused by lifetime markers + stack colouring in the past. This is intended to make sure that GISel doesn't re-introduce the bug. (This is basically a straight copy from what SelectionDAG does in SelectionDAGBuilder.cpp) https://reviews.llvm.org/D57187 llvm-svn: 352410
* [GlobalISel][AArch64] Add instruction selection support for G_FCOS and G_FSINJessica Paquette2019-01-281-1/+19
| | | | | | | | | | | | This contains all of the legalizer changes from D57197 necessary to select G_FCOS and G_FSIN. It also updates several existing IR tests in test/CodeGen/AArch64 that verify that we correctly lower the G_FCOS and G_FSIN instructions. https://reviews.llvm.org/D57197 3/3 llvm-svn: 352402
* [GlobalISel][AArch64] Add IRTranslator support for G_FCOS and G_FSINJessica Paquette2019-01-281-0/+10
| | | | | | | | | This adds IRTranslator support for the G_FCOS and G_FSIN generic instructions. https://reviews.llvm.org/D57197 2/3 llvm-svn: 352401
* [MIPS GlobalISel] Select subPetar Avramovic2019-01-281-0/+66
| | | | | | | | | Lower G_USUBO and G_USUBE. Add narrowScalar for G_SUB. Legalize and select G_SUB for MIPS 32. Differential Revision: https://reviews.llvm.org/D53416 llvm-svn: 352351
* GlobalISel: Don't reduce elements for atomic load/storeMatt Arsenault2019-01-271-1/+9
| | | | | | | This is invalid for the same reason as in the narrowScalar handling for load. llvm-svn: 352334
* GlobalISel: Factor fewerElementVectors into separate functionsMatt Arsenault2019-01-271-156/+170
| | | | llvm-svn: 352332
* [AArch64][GlobalISel] Fix the G_EXTLOAD combiner creating non-extending ↵Amara Emerson2019-01-271-0/+8
| | | | | | | | | | | | | illegal instructions. This fixes loads like 's1 = load %p (load 1 from %p)' being combined with an extend into an illegal 's8 = g_extload %p (load 1 from %p)' which doesn't do any extension, by avoiding touching those < s8 size loads. This bug was uncovered by a verifier update r351584, which I reverted it to keep the bots green. llvm-svn: 352311
* GlobalISel: Fix typo in assert messagesMatt Arsenault2019-01-271-2/+2
| | | | llvm-svn: 352301
* GlobalISel: Implement narrowScalar for mulMatt Arsenault2019-01-271-0/+47
| | | | llvm-svn: 352300
* GlobalISel: fewerElementsVector for intrinsic_trunc/intrinsic_roundMatt Arsenault2019-01-271-1/+3
| | | | llvm-svn: 352298
* [GlobalISel][IRTranslator] Fix crash on translation of fneg.Amara Emerson2019-01-261-1/+1
| | | | | | | When the fneg IR instruction was added the code to do translation wasn't tested, and tried to get an invalid operand. llvm-svn: 352296
* AMDGPU/GlobalISel: Legalize more bit opsMatt Arsenault2019-01-261-0/+3
| | | | llvm-svn: 352295
* Fix gcc -Wparentheses warning. NFCI.Simon Pilgrim2019-01-251-2/+2
| | | | llvm-svn: 352191
* AMDGPU/GlobalISel: Scalarize add/subMatt Arsenault2019-01-251-0/+1
| | | | llvm-svn: 352167
* GlobalISel: fewerElementsVector for more cast typesMatt Arsenault2019-01-251-0/+5
| | | | llvm-svn: 352166
* GlobalISel: fewerElementsVector for a few more trivial opsMatt Arsenault2019-01-251-0/+6
| | | | llvm-svn: 352165
* AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mulMatt Arsenault2019-01-251-0/+3
| | | | llvm-svn: 352162
* GlobalISel: Support fewerElementsVector for icmp/fcmpMatt Arsenault2019-01-251-3/+75
| | | | | | Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
* GlobalISel: Implement fewerElementsVector for extensionsMatt Arsenault2019-01-251-0/+54
| | | | llvm-svn: 352155
* GlobalISel: Add convenience mutatations to scalarizeMatt Arsenault2019-01-252-0/+12
| | | | llvm-svn: 352143
* RegBankSelect: Fix use after free in r352123Matt Arsenault2019-01-241-1/+1
| | | | llvm-svn: 352130
* [GISel]: Change how CSE is enabled by default for each passAditya Nandakumar2019-01-242-6/+8
| | | | | | | | | | | | | | | https://reviews.llvm.org/D57178 Now add a hook in TargetPassConfig to query if CSE needs to be enabled. By default this hook returns false only for O0 opt level but this can be overridden by the target. As a consequence of the default of enabled for non O0, a few tests needed to be updated to not use CSE (by passing in -O0) to the run line. reviewed by: arsenm llvm-svn: 352126
* RegBankSelect: Support some more complex part mappingsMatt Arsenault2019-01-242-25/+87
| | | | llvm-svn: 352123
* [GlobalISel][AArch64] Add isel support for FP16 vector @llvm.ceilJessica Paquette2019-01-241-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for vector @llvm.ceil intrinsics when full 16 bit floating point support isn't available. To do this, this patch... - Implements basic isel for G_UNMERGE_VALUES - Teaches the legalizer about 16 bit floats - Teaches AArch64RegisterBankInfo to respect floating point registers on G_BUILD_VECTOR and G_UNMERGE_VALUES - Teaches selectCopy about 16-bit floating point vectors It also adds - A legalizer test for the 16-bit vector ceil which verifies that we create a G_UNMERGE_VALUES and G_BUILD_VECTOR when full fp16 isn't supported - An instruction selection test which makes sure we lower to G_FCEIL when full fp16 is supported - A test for selecting G_UNMERGE_VALUES And also updates arm64-vfloatintrinsics.ll to show that the new ceiling types work as expected. https://reviews.llvm.org/D56682 llvm-svn: 352113
* GlobalISel: Allow shift amount to be a different typeMatt Arsenault2019-01-221-17/+47
| | | | | | | | | For AMDGPU the shift amount is never 64-bit, and this needs to use a 32-bit shift. X86 uses i8, but seemed to be hacking around this before. llvm-svn: 351882
* GlobalISel: Make buildConstant handle vectorsMatt Arsenault2019-01-221-4/+38
| | | | | | | Produce a splat build_vector similar to how SelectionDAG::getConstant does. llvm-svn: 351880
* GlobalISel: Implement widen for extract_vector_elt elt typeMatt Arsenault2019-01-221-1/+16
| | | | llvm-svn: 351871
* GlobalISel: Implement fewerElementsVector for basic FP opsMatt Arsenault2019-01-221-7/+37
| | | | llvm-svn: 351866
* GlobalISel: Support narrowing zextload/sextloadMatt Arsenault2019-01-221-0/+27
| | | | llvm-svn: 351856
* GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANTMatt Arsenault2019-01-221-4/+2
| | | | llvm-svn: 351853
* GlobalISel: Add isPointer legality predicatesMatt Arsenault2019-01-201-0/+14
| | | | llvm-svn: 351699
* GlobalISel: Implement widenScalar for basic FP opsMatt Arsenault2019-01-201-4/+13
| | | | llvm-svn: 351696
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-1922-88/+66
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [GlobalISel] Change to range-based invocation of llvm::sortMandeep Singh Grang2019-01-181-6/+3
| | | | llvm-svn: 351574
* [GISel]: Add support for CSEing continuously during GISel passes.Aditya Nandakumar2019-01-1610-72/+812
| | | | | | | | | | https://reviews.llvm.org/D52803 This patch adds support to continuously CSE instructions during each of the GISel passes. It consists of a GISelCSEInfo analysis pass that can be used by the CSEMIRBuilder. llvm-svn: 351283
* Give helper classes/functions local linkage. NFC.Benjamin Kramer2019-01-122-0/+4
| | | | llvm-svn: 351016
* GlobalISel: Implement fewerElements for implicit_defMatt Arsenault2019-01-091-0/+26
| | | | llvm-svn: 350697
* GlobalISel: Implement widenScalar for implicit_defMatt Arsenault2019-01-091-0/+6
| | | | llvm-svn: 350695
* [GlobalISel] Fix unused variable warning in Release builds.Benjamin Kramer2019-01-081-3/+3
| | | | llvm-svn: 350618
* Fix typosMatt Arsenault2019-01-081-2/+2
| | | | llvm-svn: 350597
* RegBankSelect: Fix copy insertion point for terminatorsMatt Arsenault2019-01-081-9/+15
| | | | | | | | | | | | | | | If a copy was needed to handle the condition of brcond, it was being inserted before the defining instruction. Add tests for iterator edge cases. I find the existing code here suspect for the case where it's looking for terminators that modify the register. It's going to insert a copy in the middle of the terminators, which isn't allowed (it might be necessary to have a COPY_terminator if anybody actually needs this). Also legalize brcond for AMDGPU. llvm-svn: 350595
* Add vtable anchor to classes.Richard Trieu2018-12-291-0/+4
| | | | llvm-svn: 350142
OpenPOWER on IntegriCloud