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* [globalisel][combine] Split existing rules into a match and apply stepDaniel Sanders2019-02-141-21/+39
| | | | | | | | | | | | | | | | | | | Summary: The declarative tablegen definitions split rules into match and apply steps. Prepare for that by doing the same in the C++ implementations. This aids some of the migration effort while the tablegen version is incomplete. Reviewers: bogner, volkan, aditya_nandakumar, paquette, aemerson Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, Petar.Avramovic, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58150 llvm-svn: 353996
* [GlobalISel][NFC] Gardening: Make translateSimpleUnaryIntrinsic generalJessica Paquette2019-02-121-26/+18
| | | | | | | | | | | | | | Instead of only having this code work for unary intrinsics, have it work for an arbitrary number of parameters. Factor out the cases that fall under this (fma, pow). This makes it a bit easier to add more intrinsics which don't require any special work. Differential Revision: https://reviews.llvm.org/D58079 llvm-svn: 353863
* [GlobalISel][AArch64] Select llvm.bswap* for non-vector typesJessica Paquette2019-02-121-0/+2
| | | | | | | | | | | | | | | | This teaches the IRTranslator to emit G_BSWAP when it runs into Intrinsic::bswap. This allows us to select G_BSWAP for non-vector types in AArch64. Add a select-bswap.mir test, and add global isel checks to a couple existing tests in test/CodeGen/AArch64. This doesn't handle every bswap case, since some of these rely on known bits stuff. This just lets us handle the naive case. Differential Revision: https://reviews.llvm.org/D58081 llvm-svn: 353861
* GlobalISel: Use default rounding mode when extending fconstantMatt Arsenault2019-02-121-3/+8
| | | | | | | I don't think this matters since the values should all be exactly representable. llvm-svn: 353844
* GlobalISel: Move some more legalize cases into functionsMatt Arsenault2019-02-121-165/+190
| | | | llvm-svn: 353843
* GlobalISel: Implement moreElementsVector for implicit_defMatt Arsenault2019-02-111-0/+29
| | | | llvm-svn: 353754
* GlobalISel: Fix not calling the observer when legalizing G_EXTRACTMatt Arsenault2019-02-111-0/+2
| | | | llvm-svn: 353750
* [globalisel] Correct string emitted by GISelChangeObserver::erasingInstr()Daniel Sanders2019-02-111-1/+1
| | | | | | The API indicates that the MI is about to be erased rather than it has been erased. llvm-svn: 353746
* [GlobalISel][AArch64] Select G_FFLOORJessica Paquette2019-02-111-0/+2
| | | | | | | | | | | This teaches the legalizer about G_FFLOOR, and lets us select G_FFLOOR in AArch64. It updates the existing floating point tests, and adds a select-floor.mir test. Differential Revision: https://reviews.llvm.org/D57486 llvm-svn: 353722
* Recommit "[GlobalISel] Add IRTranslator support for G_FFLOOR"Jessica Paquette2019-02-111-0/+2
| | | | | | | | | After the changes introduced in r353586, this instruction doesn't cause any issues for any backend. Original review: https://reviews.llvm.org/D57485 llvm-svn: 353720
* GlobalISel: Add G_FCANONICALIZE instructionMatt Arsenault2019-02-112-0/+4
| | | | llvm-svn: 353719
* Re-apply r353553 "[GISel][NFC]: Add missing call to record CSE hits in the ↵Francis Visoiu Mistrih2019-02-082-9/+10
| | | | | | | | CSEMIRBuilder" With a fix after r353563 that adds some more opcodes. llvm-svn: 353579
* Revert r353553 "[GISel][NFC]: Add missing call to record CSE hits in the ↵Francis Visoiu Mistrih2019-02-082-10/+9
| | | | | | | | | | | | CSEMIRBuilder" This reverts commit r353553. This breaks CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir: http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/57963/console llvm-svn: 353575
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This patch accompanies the RFC posted here: http://lists.llvm.org/pipermail/llvm-dev/2018-October/127239.html This patch adds a new CallBr IR instruction to support asm-goto inline assembly like gcc as used by the linux kernel. This instruction is both a call instruction and a terminator instruction with multiple successors. Only inline assembly usage is supported today. This also adds a new INLINEASM_BR opcode to SelectionDAG and MachineIR to represent an INLINEASM block that is also considered a terminator instruction. There will likely be more bug fixes and optimizations to follow this, but we felt it had reached a point where we would like to switch to an incremental development model. Patch by Craig Topper, Alexander Ivchenko, Mikhail Dvoretckii Differential Revision: https://reviews.llvm.org/D53765 llvm-svn: 353563
* [GISel][NFC]: Add missing call to record CSE hits in the CSEMIRBuilderAditya Nandakumar2019-02-082-9/+10
| | | | | | | | | | https://reviews.llvm.org/D57932 Add some logging + tests to make sure CSEInfo prints debug output. reviewed by: arsenm llvm-svn: 353553
* [MIPS GlobalISel] Select any extending load and truncating storePetar Avramovic2019-02-081-7/+0
| | | | | | | | | | | | | | | | | | Make behavior of G_LOAD in widenScalar same as for G_ZEXTLOAD and G_SEXTLOAD. That is perform widenScalarDst to size given by the target and avoid additional checks in common code. Targets can reorder or add additional rules in LegalizeRuleSet for the opcode to achieve desired behavior. Select extending load that does not have specified type of extension into zero extending load. Select truncating store that stores number of bytes indicated by size in MachineMemoperand. Differential Revision: https://reviews.llvm.org/D57454 llvm-svn: 353520
* AMDGPU/GlobalISel: Legalize addrspacecastMatt Arsenault2019-02-081-0/+1
| | | | | | | Use a placeholder constant for now on targets that need the load from the queue ptr. llvm-svn: 353497
* GlobalISel: Try to fix bot failuresMatt Arsenault2019-02-071-5/+5
| | | | | | Don't rely on order of evaluation of function arguments. llvm-svn: 353460
* GlobalISel: Implement narrowScalar for shift main typeMatt Arsenault2019-02-072-12/+235
| | | | | | | | | | | | | | | This is pretty much directly ported from SelectionDAG. Doesn't include the shift by non-constant but known bits version, since there isn't a globalisel version of computeKnownBits yet. This shows a disadvantage of targets not specifically which type should be used for the shift amount. If type 0 is legalized before type 1, the operations on the shift amount type use the wider type (which are also less likely to legalize). This can be avoided by targets specifying legalization actions on type 1 earlier than for type 0. llvm-svn: 353455
* GlobalISel: Implement fewerElementsVector for shiftsMatt Arsenault2019-02-071-30/+130
| | | | | | | | | Introduce a new function which handles instructions with multiple type indices, but have the same number of vector elements. Also legalize v2s16 shifts when applicable. llvm-svn: 353432
* GlobalISel: Try to make legalize rules more useful for vectorsMatt Arsenault2019-02-072-10/+49
| | | | | | | Mostly keep the existing functions on scalars, but add versions which also operate based on the vector element size. llvm-svn: 353430
* Move IR flag handling directly into builder calls for cases translated from ↵Michael Berg2019-02-061-32/+30
| | | | | | | | | | | | | | Instructions in GlobalIsel Reviewers: aditya_nandakumar, volkan Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, volkan, Petar.Avramovic Differential Revision: https://reviews.llvm.org/D57630 llvm-svn: 353336
* [GlobalISel][NFC] Gardening: Factor out code for simple unary intrinsicsJessica Paquette2019-02-061-78/+58
| | | | | | | | | | | | | There was a lot of repeated code wrt unary math intrinsics in translateKnownIntrinsic. This factors out the repeated MIRBuilder code into two functions: translateSimpleUnaryIntrinsic and getSimpleUnaryIntrinsicOpcode. This simplifies adding simple unary intrinsics, since after this, all you have to do is add the mapping to SimpleUnaryIntrinsicOpcodes. Differential Revision: https://reviews.llvm.org/D57774 llvm-svn: 353316
* GlobalISel: Consolidate load/store legalizationMatt Arsenault2019-02-051-103/+14
| | | | | | | | | | The fewerElementsVectors implementation for load/stores handles the scalar reduction case just as well, so drop the redundant code in narrowScalar. This also introduces support for narrowing irregular size breakdowns for scalars. llvm-svn: 353125
* GlobalISel: Implement narrowScalar for selectMatt Arsenault2019-02-051-0/+53
| | | | | | | | | | Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
* GlobalISel: Combine g_extract with g_merge_valuesMatt Arsenault2019-02-041-0/+1
| | | | | | | | | | | | | | Try to use the underlying source registers. This enables legalization in more cases where some irregular operations are widened and others narrowed. This seems to make the test_combines_2 AArch64 test worse, since the MERGE_VALUES has multiple uses. Since this should be required for legalization, a hasOneUse check is probably inappropriate (or maybe should only be used if the merge is legal?). llvm-svn: 353121
* GlobalISel: Fix not calling observer when legalizing bitcount opsMatt Arsenault2019-02-041-11/+12
| | | | | | This was hiding bugs from never legalizing the source type. llvm-svn: 353102
* GlobalISel: Fix CSE handling of buildConstantMatt Arsenault2019-02-042-40/+51
| | | | | | | | | | | | | | | | This fixes two problems with CSE done in buildConstant. First, this would hit an assert when used with a vector result type. Solve this by allowing CSE on the vector elements, but not on the result vector for now. Second, this was also performing the CSE based on the input ConstantInt pointer. The underlying buildConstant could potentially convert the constant depending on the result type, giving in a different ConstantInt*. Stop allowing the APInt and ConstantInt forms from automatically casting to the result type to avoid any similar problems in the future. llvm-svn: 353077
* GlobalISel: Fix moreElementsToNextPow2Matt Arsenault2019-02-042-8/+7
| | | | | | | | | This was completely broken. The condition was inverted, and changed the element type for vectors of pointers. Fixes bug 40592. llvm-svn: 353069
* Revert "[GlobalISel] Add IRTranslator support for G_FFLOOR"Jessica Paquette2019-02-041-5/+0
| | | | | | | | | This reverts commit 8bbd570fd5205a04d88d2e5513a6e4adbd028039. Apparently adding ffloor breaks AMDGPU somehow, so I need to back this out while I look into it. llvm-svn: 353064
* [GlobalISel] Add IRTranslator support for G_FFLOORJessica Paquette2019-02-041-0/+5
| | | | | | | | | | Follow-up to https://reviews.llvm.org/D57484 Adds G_FFLOOR to translateKnownIntrinsic and update arm64-irtranslator.ll. Differential Revision: https://reviews.llvm.org/D57485 llvm-svn: 353058
* GlobalISel: Fix formatting of debug outputMatt Arsenault2019-02-041-3/+3
| | | | | | | There was a missing space before the instruction name, and the newline is redundant since MI::print by default adds one. llvm-svn: 353046
* GlobalISel: Implement widenScalar for G_UNMERGE_VALUESMatt Arsenault2019-02-031-39/+83
| | | | | | | | | For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
* GlobalISel: Implement widenScalar for G_EXTRACT vector sourcesMatt Arsenault2019-02-021-0/+26
| | | | | | Handle the basic element extract case. llvm-svn: 352978
* GlobalISel: Legalization for inttoptr/ptrtointMatt Arsenault2019-02-022-4/+46
| | | | llvm-svn: 352973
* GlobalISel: Fix MMO creation with non-power-of-2 mem sizeMatt Arsenault2019-01-311-4/+5
| | | | | | | It should probably just be mandatory for getTgtMemIntrinsic to return the alignment. llvm-svn: 352817
* GlobalISel: Handle odd splits in fewerElementsVector for load/storeMatt Arsenault2019-01-311-30/+173
| | | | llvm-svn: 352720
* GlobalISel: Implement narrowScalar for bswapMatt Arsenault2019-01-311-0/+25
| | | | llvm-svn: 352719
* GlobalISel: Don't call changingInstruction before giving upMatt Arsenault2019-01-311-1/+1
| | | | llvm-svn: 352718
* GlobalISel: Allow bitcount ops to have different result typeMatt Arsenault2019-01-311-4/+30
| | | | | | For AMDGPU the result is always 32-bit for 64-bit inputs. llvm-svn: 352717
* GlobalISel: Use helper function for MMO splittingMatt Arsenault2019-01-311-14/+10
| | | | | | | | Also fix an alignment bug getMachineMemOperand. If the tracked value is null, the offset isn't tracked so the base alignment needs to be reduced. llvm-svn: 352716
* GlobalISel: Fix creating MMOs with align 0Matt Arsenault2019-01-311-1/+5
| | | | llvm-svn: 352712
* [GlobalISel][AArch64] Select G_FEXPJessica Paquette2019-01-301-1/+6
| | | | | | | | | | | | | | | This teaches the legalizer to handle G_FEXP in AArch64. As a result, it also allows us to select G_FEXP. It... - Updates the legalizer-info tests - Adds a test for legalizing exp - Updates the existing fp tests to show that we can now select G_FEXP https://reviews.llvm.org/D57483 llvm-svn: 352692
* [GlobalISel][LegalizerHelper] Add some missing MI change observer calls.Amara Emerson2019-01-301-0/+2
| | | | | | No test as it's a preventative fix. llvm-svn: 352691
* [GlobalISel][AArch64] Add instruction selection support for @llvm.log2Jessica Paquette2019-01-301-1/+7
| | | | | | | | | | | | | This teaches GlobalISel to emit a RTLib call for @llvm.log2 when it encounters it. It updates the existing floating point tests to show that we don't fall back on the intrinsic, and select the correct instructions. It also adds a legalizer test for G_FLOG2. https://reviews.llvm.org/D57357 llvm-svn: 352673
* [GlobalISel][AArch64] Add instruction selection support for @llvm.sqrtJessica Paquette2019-01-301-0/+2
| | | | | | | | | | This teaches the legalizer about G_FSQRT in AArch64. Also adds a legalizer test for G_FSQRT, a selection test for it, and updates existing floating point tests. https://reviews.llvm.org/D57361 llvm-svn: 352671
* [GlobalISel] Add IRTranslator support for @llvm.sqrt -> G_FSQRTJessica Paquette2019-01-301-0/+5
| | | | | | | | | | | Follow-up commit to https://reviews.llvm.org/D57359. (r352668) This adds IRTranslator support for recognising a @llvm.sqrt intrinsic and translating it into a G_FSQRT. https://reviews.llvm.org/D57360 llvm-svn: 352670
* GlobalISel: Add assert that legalize mutation makes senseMatt Arsenault2019-01-301-1/+64
| | | | | | | | | I've repeatedly encountered bugs resulting from custom legalize mutations returning nonsense legalize results, such as increasing the number of elements for FewerElements. Add an assert function to make sure the type to mutate to is consistent with the legalize action. llvm-svn: 352636
* GlobalISel: Implement fewerElementsVector for selectMatt Arsenault2019-01-301-0/+74
| | | | llvm-svn: 352601
* GlobalISel: Use appropriate extension for legalizing select conditionsMatt Arsenault2019-01-302-1/+22
| | | | llvm-svn: 352597
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