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* [ARM] GlobalISel: Add support for i32 moduloDiana Picus2017-06-151-17/+37
| | | | | | | | | | | | | | | | | | Add support for modulo for targets that have hardware division and for those that don't. When hardware division is not available, we have to choose the correct libcall to use. This is generally straightforward, except for AEABI. The AEABI variant is trickier than the other libcalls because it returns { quotient, remainder }, instead of just one value like the other libcalls that we've seen so far. Therefore, we need to use custom lowering for it. However, we don't want to have too much special code, so we refactor the target-independent code in the legalizer by adding a helper for replacing an instruction with a libcall. This helper is used by the legalizer itself when dealing with simple calls, and also by the custom ARM legalization for the more complicated AEABI divmod calls. llvm-svn: 305459
* [globalisel][legalizer] G_LOAD/G_STORE NarrowScalar should not emit G_GEP x, 0.Daniel Sanders2017-06-132-12/+33
| | | | | | | | | | | | | | | | | | | Summary: When legalizing G_LOAD/G_STORE using NarrowScalar, we should avoid emitting %0 = G_CONSTANT ty 0 %1 = G_GEP %x, %0 since it's cheaper to not emit the redundant instructions than it is to fold them away later. Reviewers: qcolombet, t.p.northover, ab, rovka, aditya_nandakumar, kristof.beyls Reviewed By: qcolombet Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D32746 llvm-svn: 305340
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-062-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* [GlobalISel] IRTranslator: Add MachineMemOperand to target memory intrinsicsVolkan Keles2017-06-051-0/+15
| | | | | | | | | | | | Reviewers: qcolombet, ab, t.p.northover, aditya_nandakumar, dsanders Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33724 llvm-svn: 304743
* [Localizer] Don't trick to be smart for the insertion pointQuentin Colombet2017-05-301-6/+4
| | | | | | | | | There is no guarantee that the first use of a constant that is traversed is actually the first in the related basic block. Thus, if we use that as the insertion point we may end up with definitions that don't dominate there use. llvm-svn: 304244
* [GlobalIsel] Fix a warning with GCC 7 -Wpedantic. NFCI.Davide Italiano2017-05-291-1/+1
| | | | llvm-svn: 304174
* Prune trailing whitespace. (To regenerate makefiles)NAKAMURA Takumi2017-05-281-2/+2
| | | | llvm-svn: 304112
* [GlobalISel] Add a localizer pass for target to useQuentin Colombet2017-05-273-0/+127
| | | | | | | | | | | | | This reverts commit r299287 plus clean-ups. The localizer pass is a helper pass that could be run at O0 in the GISel pipeline to work around the deficiency of the fast register allocator. It basically shortens the live-ranges of the constants so that the allocator does not spill all over the place. Long term fix would be to make the greedy allocator fast. llvm-svn: 304051
* [GlobalISel] IRTranslator: Translate ConstantStructVolkan Keles2017-05-191-0/+26
| | | | | | | | | | | | Reviewers: qcolombet, ab, t.p.northover, aditya_nandakumar, dsanders Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33317 llvm-svn: 303412
* Re-commit: [globalisel][tablegen] Import rules containing intrinsic_wo_chain.Daniel Sanders2017-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 The previous commit failed on test-suite/Bitcode/simd_ops/AArch64_halide_runtime.bc because isImmOperandEqual() assumed MO was a register operand and that's not always true. llvm-svn: 303341
* [GISel]: Fix undefined behavior in IRTranslatorAditya Nandakumar2017-05-171-0/+5
| | | | | | | | Make sure IRTranslator->MachineIRBuilder->DebugLoc doesn't outlive the DILocation. Clear it at the end of IRTranslator::runOnMachineFunction llvm-svn: 303277
* [RegisterBankInfo] Remove overly-agressive assertsTom Stellard2017-05-151-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | Summary: We were asserting in RegisterBankInfo if RBI.copyCost() returns UINT_MAX. This is OK for RegBankSelect::Mode::Fast since we only try one instruction mapping and can't recover from this, but for RegBankSelect::Mode::Greedy we will be considering multiple instruction mappings, so we can recover if we see a UNIT_MAX copy cost. The copy cost for one pair of register banks in the AMDGPU backend will be UNIT_MAX, so this patch will prevent AMDGPU tests from breaking. Reviewers: ab, qcolombet, t.p.northover, dsanders Reviewed By: qcolombet Subscribers: tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D33144 llvm-svn: 303043
* [GISel]: Add a getConstantFPVRegVal utilityAditya Nandakumar2017-05-121-0/+8
| | | | | | | | This might be useful across various GISel Passes https://reviews.llvm.org/D33051 llvm-svn: 302964
* [GISel]: Fix undefined behavior while accessing DefaultAction mapAditya Nandakumar2017-05-121-1/+1
| | | | | | | | We end up dereferencing the end iterator here when the Aspect doesn't exist in the DefaultAction map. Change the API to return Optional<LLT> and return None when not found. Also update the callers to handle the None case llvm-svn: 302963
* [GISel]: Remove unused lambda captures. NFCAditya Nandakumar2017-05-111-4/+4
| | | | | | https://reviews.llvm.org/D33085 llvm-svn: 302831
* [RegisterBankInfo] Uniquely allocate instruction mapping.Quentin Colombet2017-05-052-28/+68
| | | | | | | | | | This is a step toward having statically allocated instruciton mapping. We are going to tablegen them eventually, so let us reflect that in the API. NFC. llvm-svn: 302316
* ARM: Compute MaxCallFrame size earlyMatthias Braun2017-05-052-5/+5
| | | | | | | | | | | | | | | | | This exposes a method in MachineFrameInfo that calculates MaxCallFrameSize and calls it after instruction selection in the ARM target. This avoids ARMBaseRegisterInfo::canRealignStack()/ARMFrameLowering::hasReservedCallFrame() giving different answers in early/late phases of codegen. The testcase shows a particular nasty example result of that where we would fail to properly align an alloca. Differential Revision: https://reviews.llvm.org/D32622 llvm-svn: 302303
* [GISel]:Skip legalizing Intermediate inst(with generic types)Aditya Nandakumar2017-05-041-2/+7
| | | | | | | | | | During legalization, targets can create Pseudo Instructions with generic types. We shouldn't try to legalize them. Reviewed by Quentin, dsanders https://reviews.llvm.org/D32575 llvm-svn: 302199
* [GISel]: Add support to translate ConstantVectorsAditya Nandakumar2017-05-041-0/+8
| | | | | | | Reviewed by Quentin https://reviews.llvm.org/D32814 llvm-svn: 302196
* [IR] Abstract away ArgNo+1 attribute indexing as much as possibleReid Kleckner2017-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Do three things to help with that: - Add AttributeList::FirstArgIndex, which is an enumerator currently set to 1. It allows us to change the indexing scheme with fewer changes. - Add addParamAttr/removeParamAttr. This just shortens addAttribute call sites that would otherwise need to spell out FirstArgIndex. - Remove some attribute-specific getters and setters from Function that take attribute list indices. Most of these were only used from BuildLibCalls, and doesNotAlias was only used to test or set if the return value is malloc-like. I'm happy to split the patch, but I think they are probably easier to review when taken together. This patch should be NFC, but it sets the stage to change the indexing scheme to this, which is more convenient when indexing into an array: 0: func attrs 1: retattrs 2...: arg attrs Reviewers: chandlerc, pete, javed.absar Subscribers: david2050, llvm-commits Differential Revision: https://reviews.llvm.org/D32811 llvm-svn: 302060
* Re-land r301697 "[IR] Make add/remove Attributes use AttrBuilder instead of ↵Reid Kleckner2017-05-021-2/+2
| | | | | | | | | | AttributeList" This time, I fixed, built, and tested clang. This reverts r301712. llvm-svn: 301981
* [globalisel][tablegen] Compute available feature bits correctly.Daniel Sanders2017-04-291-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Predicate<> now has a field to indicate how often it must be recomputed. Currently, there are two frequencies, per-module (RecomputePerFunction==0) and per-function (RecomputePerFunction==1). Per-function predicates are currently recomputed more frequently than necessary since the only predicate in this category is cheap to test. Per-module predicates are now computed in getSubtargetImpl() while per-function predicates are computed in selectImpl(). Tablegen now manages the PredicateBitset internally. It should only be necessary to add the required includes. Also fixed a problem revealed by the test case where constrainSelectedInstRegOperands() would attempt to tie operands that BuildMI had already tied. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32491 llvm-svn: 301750
* Revert r301697 "[IR] Make add/remove Attributes use AttrBuilder instead of ↵Hans Wennborg2017-04-281-2/+2
| | | | | | | | | | | | | | | | | | AttributeList" This broke the Clang build. (Clang-side patch missing?) Original commit message: > [IR] Make add/remove Attributes use AttrBuilder instead of > AttributeList > > This change cleans up call sites and avoids creating temporary > AttributeList objects. > > NFC llvm-svn: 301712
* [IR] Make add/remove Attributes use AttrBuilder instead of AttributeListReid Kleckner2017-04-281-2/+2
| | | | | | | | | This change cleans up call sites and avoids creating temporary AttributeList objects. NFC llvm-svn: 301697
* Make getParamAlignment use argument numbersReid Kleckner2017-04-281-2/+2
| | | | | | | | | | | | | | | | | | The method is called "get *Param* Alignment", and is only used for return values exactly once, so it should take argument indices, not attribute indices. Avoids confusing code like: IsSwiftError = CS->paramHasAttr(ArgIdx, Attribute::SwiftError); Alignment = CS->getParamAlignment(ArgIdx + 1); Add getRetAlignment to handle the one case in Value.cpp that wants the return value alignment. This is a potentially breaking change for out-of-tree backends that do their own call lowering. llvm-svn: 301682
* GlobalISel: Followup for r301679Matthias Braun2017-04-281-1/+2
| | | | llvm-svn: 301681
* TargetLowering: Add finalizeLowering() function; NFCMatthias Braun2017-04-281-3/+1
| | | | | | | | | | | | | | | | | Adds a new method finalizeLowering to TargetLoweringBase. This is in preparation for an upcoming commit. This function is meant for target specific adjustments to MachineFrameInfo or register reservations. Move the freezeRegisters() and the hasCopyImplyingStackAdjustment() handling into the new function to prove the concept. As an added bonus GlobalISel no longer missed the hasCopyImplyingStackAdjustment() handling with this. Differential Revision: https://reviews.llvm.org/D32621 llvm-svn: 301679
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-243-3/+5
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* [GlobalISel] Legalize G_(S|U)DIV libcallsDiana Picus2017-04-241-12/+30
| | | | | | | | | | Treat them the same as the other binary operations that we have so far, but on integers rather than floating point types. Extract the common code into a helper. This will be used in the ARM backend. llvm-svn: 301163
* Fix use-after-frees on memory allocated in a Recycler.Benjamin Kramer2017-04-201-1/+5
| | | | | | | | This will become asan errors once the patch lands that poisons the memory after free. The x86 change is a hack, but I don't see how to solve this properly at the moment. llvm-svn: 300867
* [globalisel] Enable tracing the legalizer with --debug-only=legalize-mirDaniel Sanders2017-04-202-6/+32
| | | | | | | | | | | | Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka, kristof.beyls Reviewed By: kristof.beyls Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31750 llvm-svn: 300847
* [GISEL]: Move getConstantVReg to UtilsAditya Nandakumar2017-04-192-17/+17
| | | | | | NFCI llvm-svn: 300751
* [GlobalISel] Support vector-of-pointers in LLTKristof Beyls2017-04-191-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes PR32471. As comment 10 on that bug report highlights (https://bugs.llvm.org//show_bug.cgi?id=32471#c10), there are quite a few different defendable design tradeoffs that could be made, including not representing pointers at all in LLT. I decided to go for representing vector-of-pointer as a concept in LLT, while keeping the size of the LLT type 64 bits (this is an increase from 48 bits before). My rationale for keeping pointers explicit is that on some targets probably it's very handy to have the distinction between pointer and non-pointer (e.g. 68K has a different register bank for pointers IIRC). If we keep a scalar pointer, it probably is easiest to also have a vector-of-pointers to keep LLT relatively conceptually clean and orthogonal, while we don't have a very strong reason to break that orthogonality. Once we gain more experience on the use of LLT, we can of course reconsider this direction. Rejecting vector-of-pointer types in the IRTranslator is also an option to avoid the crash reported in PR32471, but that is only a very short-term solution; also needs quite a bit of code tweaks in places, and is probably fragile. Therefore I didn't consider this the best option. llvm-svn: 300664
* [GlobalISel] Remove non-determinism from IRTranslator.Kristof Beyls2017-04-191-12/+16
| | | | | | | | | | | This showed up in r300535/r300537, which were reverted in r300538 due to some of the introduced tests in there failing on some bots, due to the non-determinism fixed in this commit. Re-committing r300535/r300537 will add 2 tests for the change in this commit. llvm-svn: 300663
* Revert "[GlobalISel] Support vector-of-pointers in LLT"Kristof Beyls2017-04-181-3/+2
| | | | | | | | | | | | | | | | This reverts r300535 and r300537. The newly added tests in test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll produces slightly different code between LLVM versions being built with different compilers. E.g., dependent on the compiler LLVM is built with, either one of the following can be produced: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(p0) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg2; (in function: vector_of_pointers_extractelement) remark: <unknown>:0:0: unable to legalize instruction: %vreg2<def>(p0) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg0; (in function: vector_of_pointers_extractelement) Non-determinism like this is clearly a bad thing, so reverting this until I can find and fix the root cause of the non-determinism. llvm-svn: 300538
* [GlobalISel] Support vector-of-pointers in LLTKristof Beyls2017-04-181-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes PR32471. As comment 10 on that bug report highlights (https://bugs.llvm.org//show_bug.cgi?id=32471#c10), there are quite a few different defendable design tradeoffs that could be made, including not representing pointers at all in LLT. I decided to go for representing vector-of-pointer as a concept in LLT, while keeping the size of the LLT type 64 bits (this is an increase from 48 bits before). My rationale for keeping pointers explicit is that on some targets probably it's very handy to have the distinction between pointer and non-pointer (e.g. 68K has a different register bank for pointers IIRC). If we keep a scalar pointer, it probably is easiest to also have a vector-of-pointers to keep LLT relatively conceptually clean and orthogonal, while we don't have a very strong reason to break that orthogonality. Once we gain more experience on the use of LLT, we can of course reconsider this direction. Rejecting vector-of-pointer types in the IRTranslator is also an option to avoid the crash reported in PR32471, but that is only a very short-term solution; also needs quite a bit of code tweaks in places, and is probably fragile. Therefore I didn't consider this the best option. llvm-svn: 300535
* GlobalISel: Allow legalizing G_FADD to a libcallDiana Picus2017-04-111-0/+4
| | | | | | | | | Use the same handling in the generic legalizer code as for the other libcalls (G_FREM, G_FPOW). Enable it on ARM for float and double so we can test it. llvm-svn: 299931
* [GlobalISel] LegalizerInfo: Enable legalization of non-power-of-2 typesVolkan Keles2017-04-111-6/+9
| | | | | | | | | | | | | | Summary: Legalize only if the type is marked as Legal or Custom. If not, return Unsupported as LegalizerHelper is not able to handle non-power-of-2 types right now. Reviewers: qcolombet, aditya_nandakumar, dsanders, t.p.northover, kristof.beyls, javed.absar, ab Reviewed By: kristof.beyls, ab Subscribers: dberris, rovka, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31711 llvm-svn: 299929
* [GlobalISel]: Fix bug where we can report GISelFailure on erased instructionsAditya Nandakumar2017-04-072-38/+26
| | | | | | | | | | | | | The original instruction might get legalized and erased and expanded into intermediate instructions and the intermediate instructions might fail legalization. This end up in reporting GISelFailure on the erased instruction. Instead report GISelFailure on the intermediate instruction which failed legalization. Reviewed by: ab llvm-svn: 299802
* [GlobalISel] implement narrowing for G_CONSTANT.Igor Breger2017-04-071-0/+20
| | | | | | | | | | | | | | Summary: [GlobalISel] implement narrowing for G_CONSTANT. Reviewers: bogner, zvi, t.p.northover Reviewed By: t.p.northover Subscribers: llvm-commits, dberris, rovka, kristof.beyls Differential Revision: https://reviews.llvm.org/D31744 llvm-svn: 299772
* [tablegen][globalisel] Add support for nested instruction matching.Daniel Sanders2017-04-041-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
* Revert "Localizer fun"Quentin Colombet2017-04-013-122/+0
| | | | | | | | This reverts commit r299283. Didn't intend to commit this :( llvm-svn: 299287
* [RegBankSelect] Support REG_SEQUENCE for generic mappingQuentin Colombet2017-04-011-8/+18
| | | | | | | | | | | | | | | | REG_SEQUENCE falls into the same category as COPY for operands mapping: - They don't have MCInstrDesc with register constraints - The input variable could use whatever register classes - It is possible to have register class already assigned to the operands In particular, given REG_SEQUENCE are always target specific because of the subreg indices. Those indices must apply to the register class of the definition of the REG_SEQUENCE and therefore, the target must set a register class to that definition. As a result, the generic code can always use that register class to derive a valid mapping for a REG_SEQUENCE. llvm-svn: 299285
* Localizer funQuentin Colombet2017-04-013-0/+122
| | | | | | WIP llvm-svn: 299283
* [GlobalISel] Add a 'getConstantVRegVal' helper.Ahmed Bougacha2017-03-271-12/+20
| | | | | | Use it to compare immediate operands. llvm-svn: 298855
* [GlobalISel]: Create VREGs for ConstantInt argsAditya Nandakumar2017-03-221-4/+1
| | | | | | | | | | | | This patch changes the behavior of IRTranslating intrinsics where we now create VREG + G_CONSTANT for ConstantInt values. We already do this for FloatingPoint values. This makes it easier for the backends to select code and it won't have to de-duplicate creation+selection of constants. Reviewed by: ab llvm-svn: 298473
* [GlobalISel] Update DBG_VALUEs referencing DCE'd instructions.Ahmed Bougacha2017-03-212-3/+3
| | | | | | | | | | | | | Quentin points out that r298358 would cause us to emit different code with debug info. That's a big no-no; also erase the instructions that only live thanks to DBG_VALUE users. Adrian explained how this is an existing problem and an OK thing to do: clang has allocas for all variables so shouldn't be affected at -O0, but swift uses a bit of inlineasm to explicitly keep values live for the purpose of debug info quality. I'm not sure there is a better scheme. llvm-svn: 298460
* [GlobalISel] Don't translate br to layout successor.Ahmed Bougacha2017-03-211-2/+5
| | | | | | | | | | MI can represent fallthrough to layout successor blocks, and our post-isel representation uses that extensively. We might as well use it too, to avoid translating and carrying along unnecessary branches. llvm-svn: 298459
* GlobalISel: respect BooleanContents when extending i1.Tim Northover2017-03-211-4/+16
| | | | | | | The world isn't just x86 & ARM, some targets need to store -1 into the byte when legalizing a bool store. llvm-svn: 298453
* GlobalISel: widen booleans by zero-extending to a byte.Tim Northover2017-03-211-1/+1
| | | | | | | A bool is represented by a single byte, which the ARM ABI requires to be either 0 or 1. So we cannot use G_ANYEXT when legalizing the type. llvm-svn: 298439
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