summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/GlobalISel/Utils.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-1/+1
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* GlobalISel: Use a callback to compute constrained reg class for unallocatble ↵Tom Stellard2018-05-031-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | registers Summary: constrainOperandRegClass() currently fails if it tries to constrain the register class of an operand that is defeined with an unallocatable register class. This patch resolves this by adding a target callback to compute register constriants in this case. This is required by the AMDGPU because many of its instructions have source opreands defined with the unallocatable register classe VS_32 which is a union of two allocatable register classes VGPR_32 and SReg_32. Reviewers: dsanders, aditya_nandakumar Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D45991 llvm-svn: 331485
* [GISel]: Add helpers for easy building G_FCONSTANT along with matchersAditya Nandakumar2018-03-091-0/+14
| | | | | | | | | | | | | | | | | | Added helpers to build G_FCONSTANT, along with matching ConstantFP and unit tests for the same. Sample usage. auto MIB = Builder.buildFConstant(s32, 0.5); // Build IEEESingle For Matching the above const ConstantFP* Tmp; mi_match(DstReg, MRI, m_GFCst(Tmp)); https://reviews.llvm.org/D44128 reviewed by: volkan llvm-svn: 327152
* [GISel]: Print more fallback information when abortingAditya Nandakumar2018-02-271-1/+1
| | | | | | | | | | | | Currently when abort is enabled, we get a diagnostic saying "Fallback path used .... " and the program terminates. To actually figure out what the reason is, we need to run again with another verbose argument "-pass-remarks-missed=gisel". Instead, when we are going to abort, we might as well print expensive remarks. https://reviews.llvm.org/D43796 llvm-svn: 326215
* [GISel]: Don't assert when constraining RegisterOperands which are uses.Aditya Nandakumar2018-02-261-7/+9
| | | | | | | | | | | | | Currently we assert that only non target specific opcodes can have missing RegisterClass constraints in the MCDesc. The backend can have instructions with register operands but don't have RegisterClass constraints (say using unknown_class) in which case the instruction defining the register will constrain it. Change the assert to only fire if a def has no regclass. https://reviews.llvm.org/D43409 llvm-svn: 326142
* [ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from ↵Daniel Sanders2018-01-291-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Dst Pattern Summary: Apparently, we missed on constraining register classes of VReg-operands of all the instructions built from a destination pattern but the root (top-level) one. The issue exposed itself while selecting G_FPTOSI for armv7: the corresponding pattern generates VTOSIZS wrapped into COPY_TO_REGCLASS, so top-level COPY_TO_REGCLASS gets properly constrained, while nested VTOSIZS (or rather its destination virtual register to be exact) does not. Fixing this by issuing GIR_ConstrainSelectedInstOperands for every nested GIR_BuildMI. https://bugs.llvm.org/show_bug.cgi?id=35965 rdar://problem/36886530 Patch by Roman Tereshin Reviewers: dsanders, qcolombet, rovka, bogner, aditya_nandakumar, volkan Reviewed By: dsanders, qcolombet, rovka Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42565 llvm-svn: 323692
* [GISel] Make constrainSelectedInstRegOperands() available to the legalizer. NFCAditya Nandakumar2018-01-171-0/+45
| | | | | | https://reviews.llvm.org/D42149 llvm-svn: 322743
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [GISel][NFC]: Move getOpcodeDef from the LegalizationArtifactCombiner into ↵Aditya Nandakumar2017-11-151-0/+16
| | | | | | GlobalISel/Utils for use elsewhere llvm-svn: 318350
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* [GlobalISel] Only build expensive remarks if they're enabled. NFC.Ahmed Bougacha2017-09-181-1/+4
| | | | | | | | r313390 taught 'allowExtraAnalysis' to check whether remarks are enabled at all. Use that to only do the expensive instruction printing if they are. llvm-svn: 313552
* [globalisel][tablegen] Add support for COPY_TO_REGCLASS.Daniel Sanders2017-06-201-10/+18
| | | | | | | | | | | | | | | | | | | | | | Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
* [GISel]: Add a getConstantFPVRegVal utilityAditya Nandakumar2017-05-121-0/+8
| | | | | | | | This might be useful across various GISel Passes https://reviews.llvm.org/D33051 llvm-svn: 302964
* [GISEL]: Move getConstantVReg to UtilsAditya Nandakumar2017-04-191-0/+17
| | | | | | NFCI llvm-svn: 300751
* [GlobalISel] Update DBG_VALUEs referencing DCE'd instructions.Ahmed Bougacha2017-03-211-2/+2
| | | | | | | | | | | | | Quentin points out that r298358 would cause us to emit different code with debug info. That's a big no-no; also erase the instructions that only live thanks to DBG_VALUE users. Adrian explained how this is an existing problem and an OK thing to do: clang has allocas for all variables so shouldn't be affected at -O0, but swift uses a bit of inlineasm to explicitly keep values live for the purpose of debug info quality. I'm not sure there is a better scheme. llvm-svn: 298460
* [GlobalISel] Move isTriviallyDead to Utils. NFC.Volkan Keles2017-03-211-0/+21
| | | | | | Make it accessible by the targets to avoid code duplication. llvm-svn: 298358
* [GlobalISel] Emit opt remarks on isel fallbacks.Ahmed Bougacha2017-02-231-0/+29
| | | | | | | | | | | | | | | | | Having more fine-grained information on the specific construct that caused us to fallback is valuable for large-scale data collection. We still have the fallback warning, that's also used for FastISel. We still need to remove the fallback warning, and teach FastISel to also emit remarks (it currently has a combination of the warning, stats, and debug prints: the remarks could unify all three). The abort-on-fallback path could also be better handled using remarks: one could imagine a "-Rpass-error", analoguous to "-Werror", which would promote missed/failed remarks to errors. It's not clear whether that would be useful for other remarks though, so we're not there yet. llvm-svn: 296013
* [GlobalISel] Refactor the logic to constraint registers.Quentin Colombet2016-12-221-0/+45
Move the logic to constraint register from InstructionSelector to a utility function. It will be required by other passes in the GlobalISel pipeline. llvm-svn: 290374
OpenPOWER on IntegriCloud