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* ARM: Compute MaxCallFrame size earlyMatthias Braun2017-05-051-2/+5
| | | | | | | | | | | | | | | | | This exposes a method in MachineFrameInfo that calculates MaxCallFrameSize and calls it after instruction selection in the ARM target. This avoids ARMBaseRegisterInfo::canRealignStack()/ARMFrameLowering::hasReservedCallFrame() giving different answers in early/late phases of codegen. The testcase shows a particular nasty example result of that where we would fail to properly align an alloca. Differential Revision: https://reviews.llvm.org/D32622 llvm-svn: 302303
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-1/+3
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* [GlobalISel] Update DBG_VALUEs referencing DCE'd instructions.Ahmed Bougacha2017-03-211-1/+1
| | | | | | | | | | | | | Quentin points out that r298358 would cause us to emit different code with debug info. That's a big no-no; also erase the instructions that only live thanks to DBG_VALUE users. Adrian explained how this is an existing problem and an OK thing to do: clang has allocas for all variables so shouldn't be affected at -O0, but swift uses a bit of inlineasm to explicitly keep values live for the purpose of debug info quality. I'm not sure there is a better scheme. llvm-svn: 298460
* [GlobalISel] Move isTriviallyDead to Utils. NFC.Volkan Keles2017-03-211-23/+0
| | | | | | Make it accessible by the targets to avoid code duplication. llvm-svn: 298358
* [GlobalISel] Don't select trivially dead instructions.Ahmed Bougacha2017-03-191-0/+31
| | | | | | | | | | | | | | Folding instructions when selecting can cause them to become dead. Don't select these dead instructions (if they don't have other side effects, and don't define physical registers). Preserve existing tests by adding COPYs. In some tests, the G_CONSTANT vregs never get constrained to a class: the only use of the vreg was folded into another instruction, so the G_CONSTANT, now dead, never gets selected. llvm-svn: 298224
* [GlobalISel] Move method definition to the proper file. NFC.Ahmed Bougacha2017-03-191-19/+0
| | | | llvm-svn: 298221
* GlobalISel: check for CImm rather than Imm on G_CONSTANTs.Tim Northover2017-02-241-2/+5
| | | | | | | All G_CONSTANTS created by the MachineIRBuilder have an operand of type CImm (i.e. a ConstantInt), so that's what the selector needs to look for. llvm-svn: 296176
* [globalisel] Decouple src pattern operands from dst pattern operands.Daniel Sanders2017-02-241-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
* [GlobalISel] Use the DISubprogram for translation failure remarks.Ahmed Bougacha2017-02-241-1/+2
| | | | | | | Justin added support for DISubprogram locs in r295531 and r296052. Use that instead of no-loc for constants and arguments. llvm-svn: 296058
* [GlobalISel] Emit opt remarks on isel fallbacks.Ahmed Bougacha2017-02-231-30/+24
| | | | | | | | | | | | | | | | | Having more fine-grained information on the specific construct that caused us to fallback is valuable for large-scale data collection. We still have the fallback warning, that's also used for FastISel. We still need to remove the fallback warning, and teach FastISel to also emit remarks (it currently has a combination of the warning, stats, and debug prints: the remarks could unify all three). The abort-on-fallback path could also be better handled using remarks: one could imagine a "-Rpass-error", analoguous to "-Werror", which would promote missed/failed remarks to errors. It's not clear whether that would be useful for other remarks though, so we're not there yet. llvm-svn: 296013
* [GlobalISel] Simplify Select type cleanup using a ScopeExit. NFC.Ahmed Bougacha2017-02-231-13/+18
| | | | | | This lets us use more natural early-returns when selection fails. llvm-svn: 296006
* GlobalISel: tidy up def/use test. NFC.Tim Northover2017-01-301-2/+2
| | | | llvm-svn: 293545
* GlobalISel: permit unused vregs without a register-class after ISel.Tim Northover2017-01-301-5/+9
| | | | | | | This can happen if earlier combining has removed all uses of some VReg, which is fine and shouldn't flag an error. llvm-svn: 293537
* GlobalISel: Fix typo in error messageJustin Bogner2017-01-251-1/+1
| | | | llvm-svn: 293023
* GlobalISel: Pass the MachineFunction in to reportSelectionError directlyJustin Bogner2017-01-201-6/+6
| | | | | | | | Rather than trying to find MF based on the possibly-null MI we've passed in here, just pass it in directly. It's already available at all callers anyway. llvm-svn: 292544
* GlobalISel: Fix text wrapping in a comment. NFCJustin Bogner2017-01-191-2/+1
| | | | llvm-svn: 292460
* GlobalISel: Fix unconditional fallback with global isel abort is disabledTom Stellard2016-11-181-1/+1
| | | | | | | | | | Reviewers: t.p.northover, ab, qcolombet Subscribers: mehdi_amini, vkalintiris, wdng, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D26765 llvm-svn: 287344
* GlobalISel: make sure debugging variables are appropriately elided in ↵David L. Jones2016-11-081-2/+4
| | | | | | | | | | | | | | | | release builds. Summary: There are two variables here that break. This change constrains both of them to debug builds (via DEBUG() or #ifndef NDEBUG). Reviewers: bkramer, t.p.northover Subscribers: mehdi_amini, vkalintiris Differential Revision: https://reviews.llvm.org/D26421 llvm-svn: 286300
* GlobalISel: allow CodeGen to fallback on VReg type/class issues.Tim Northover2016-11-081-14/+38
| | | | | | | | | After instruction selection we perform some checks on each VReg just before discarding the type information. These checks were assertions before, but that breaks the fallback path so this patch moves the logic into the main flow and reports a better error on failure. llvm-svn: 286289
* [GlobalISel] Dump all instructions inserted by selector.Ahmed Bougacha2016-11-081-3/+9
| | | | | | This is helpful when multiple instructions are inserted. llvm-svn: 286273
* [GlobalISel] Permit select() to erase.Ahmed Bougacha2016-11-081-5/+22
| | | | | | | | | | | Erasing reverse_iterators is problematic; iterate manually. While there, keep track of the range of inserted instructions. It can miss instructions inserted elsewhere, but those are harder to track. Differential Revision: http://reviews.llvm.org/D22924 llvm-svn: 286272
* GlobalISel: rename legalizer components to match others.Tim Northover2016-10-141-3/+3
| | | | | | | | | | The previous names were both misleading (the MachineLegalizer actually contained the info tables) and inconsistent with the selector & translator (in having a "Machine") prefix. This should make everything sensible again. The only functional change is the name of a couple of command-line options. llvm-svn: 284287
* GlobalISel: move type information to MachineRegisterInfo.Tim Northover2016-09-091-2/+3
| | | | | | | | | | | | | | | | | We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
* [InstructionSelect] NumBlocks isn't defined in DEBUG build.Haojian Wu2016-08-291-1/+1
| | | | | | | | | | | | Summary: A follow-up fixing on http://llvm.org/viewvc/llvm-project?view=revision&revision=279905. Reviewers: bkramer Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D23985 llvm-svn: 279959
* [InstructionSelect] Do not abort when the target wants to fall back.Quentin Colombet2016-08-271-7/+28
| | | | llvm-svn: 279905
* [GlobalISel] Teach the core pipeline not to run if ISel failed.Quentin Colombet2016-08-271-0/+5
| | | | llvm-svn: 279889
* [GlobalISel] Set the Selected MF property.Ahmed Bougacha2016-08-021-14/+0
| | | | | | | None of GlobalISel requires the property, but this lets us use the verifier instead of rolling our own "all instructions selected" check. llvm-svn: 277484
* [GlobalISel] Set, require, and verify Legalized MF property.Ahmed Bougacha2016-08-021-0/+14
| | | | | | | | | | | | | RegBankSelect and InstructionSelect run after the legalizer and require a Legalized function: check that all instructions are legal. Note that this should be in the MachineVerifier, but it can't use the MachineLegalizer as it's currently in the separate GlobalISel library. Note that the RegBankSelect verifier checks have the same layering problem, but we only use inline methods so end up not needing to link against the GlobalISel library. llvm-svn: 277472
* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-271-0/+99
And implement it for AArch64, supporting x/w ADD/OR. Differential Revision: https://reviews.llvm.org/D22373 llvm-svn: 276875
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