summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/ExecutionDepsFix.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Add opt-bisect support to additional passes that can be skippedAndrew Kaylor2016-05-031-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D19882 llvm-svn: 268457
* livePhysRegs: Pass MBB by reference in addLive{Ins|Outs}(); NFCMatthias Braun2016-05-031-1/+1
| | | | | | | The block must no be nullptr for the addLiveIns()/addLiveOuts() function. llvm-svn: 268340
* LivePhysRegs: Automatically determine presence of pristine regs.Matthias Braun2016-05-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | Remove the AddPristinesAndCSRs parameters from addLiveIns()/addLiveOuts(). We need to respect pristine registers after prologue epilogue insertion, Seeing that we got this wrong in at least two commits already, we should rather pay the small price to query MachineFrameInfo for it. There are three cases that did not set AddPristineAndCSRs to true even after register allocation: - ExecutionDepsFix: live-out registers are used as a hint that the register is used soon. This is not true for pristine registers so use the new addLiveOutsNoPristines() to maintain this behaviour. - SystemZShortenInst: Not setting AddPristineAndCSRs to true looks like a bug, should do the right thing automatically now. - StackMapLivenessAnalysis: Not adding pristine registers looks like a bug to me. Added a FIXME comment but maintain the current behaviour as a change may need to get coordinated with GC runtimes. llvm-svn: 268336
* Add MachineFunctionProperty checks for AllVRegsAllocated for target passesDerek Schuff2016-04-041-0/+5
| | | | | | | | | | | | | | Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocation. Reviewers: qcolombet Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18525 llvm-svn: 265313
* use range-based for-loops; NFCISanjay Patel2015-12-291-9/+6
| | | | llvm-svn: 256566
* CodeGen: Start removing implicit conversions to/from list iterators, NFCDuncan P. N. Exon Smith2015-10-091-1/+1
| | | | | | | Start removing implicit conversions to/from list iterators in CodeGen, ala r249782 for IR. A lot more to go after this. llvm-svn: 249851
* Save LaneMask with livein registersMatthias Braun2015-09-091-2/+2
| | | | | | | | | | | | | | | | | With subregister liveness enabled we can detect the case where only parts of a register are live in, this is expressed as a 32bit lanemask. The current code only keeps registers in the live-in list and therefore enumerated all subregisters affected by the lanemask. This turned out to be too conservative as the subregister may also cover additional parts of the lanemask which are not live. Expressing a given lanemask by enumerating a minimum set of subregisters is computationally expensive so the best solution is to simply change the live-in list to store the lanemasks as well. This will reduce memory usage for targets using subregister liveness and slightly increase it for other targets Differential Revision: http://reviews.llvm.org/D12442 llvm-svn: 247171
* MachineBasicBlock: Add liveins() method returning an iterator_rangeMatthias Braun2015-08-241-3/+2
| | | | llvm-svn: 245895
* MachineRegisterInfo: Introduce isPhysRegUsed()Matthias Braun2015-08-181-7/+6
| | | | | | | | | | | | | | | | This method checks whether a physical regiser or any of its aliases are used in the function. Using this function in SIRegisterInfo::findUnusedReg() should also fix this reported failure: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20150803/292143.html http://reviews.llvm.org/rL242173#inline-533 The report doesn't come with a testcase and I don't know enough about AMDGPU to create one myself. llvm-svn: 245329
* Use make_range(rbegin(), rend()) to allow foreach loops. NFC.Pete Cooper2015-07-241-4/+3
| | | | | | | | | | | Instead of the pattern for (auto I = x.rbegin(), E = x.end(); I != E; ++I) we can use make_range to construct the reverse range and iterate using that instead. llvm-svn: 243163
* MachineRegisterInfo: Remove UsedPhysReg infrastructureMatthias Braun2015-07-141-5/+7
| | | | | | | | | | | | | We have a detailed def/use lists for every physical register in MachineRegisterInfo anyway, so there is little use in maintaining an additional bitset of which ones are used. Removing it frees us from extra book keeping. This simplifies VirtRegMap. Differential Revision: http://reviews.llvm.org/D10911 llvm-svn: 242173
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-2/+2
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-2/+2
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* remove function names from comments; NFCSanjay Patel2015-03-151-7/+6
| | | | llvm-svn: 232328
* fix typo: NFCSanjay Patel2015-03-151-1/+1
| | | | llvm-svn: 232327
* ExecutionDepsFix: Indizes -> Indices.Matthias Braun2015-03-061-10/+10
| | | | | | Translate german to english. llvm-svn: 231500
* Fix typo.Eric Christopher2015-03-061-1/+1
| | | | llvm-svn: 231495
* ExecutionDepsFix: Correctly handle wide registers.Matthias Braun2014-12-171-70/+71
| | | | | | | | | | | | | | The ExecutionDepsFix previously mapped each register to 1 or zero registers of the register class it was called with and therefore simulating liveness for. This was problematic for cases involving wider registers like Q0 on ARM where ExecutionDepsFix gets invoked for the Dxx registers. In these cases the wide register would get mapped to the last matching D register, while it should have been all matching D registers. This commit changes the AliasMap to use a SmallVector to map registers to potentially multiple destination regclass registers. This is required to avoid regressions with subregister liveness tracking enabled. llvm-svn: 224447
* Fixing -Wsign-compare warnings; NFC.Aaron Ballman2014-12-161-1/+2
| | | | llvm-svn: 224337
* Silence more static analyzer warnings.Michael Ilseman2014-12-151-4/+11
| | | | | | | | Add in definedness checks for shift operators, null checks when pointers are assumed by the code to be non-null, and explicit unreachables. llvm-svn: 224255
* Move register class name strings to a single array in MCRegisterInfo to ↵Craig Topper2014-11-171-1/+1
| | | | | | | | reduce static table size and number of relocation entries. Indices into the table are stored in each MCRegisterClass instead of a pointer. A new method, getRegClassName, is added to MCRegisterInfo and TargetRegisterInfo to lookup the string in the table. llvm-svn: 222118
* Remove unnecessary TargetMachine.h includes.Eric Christopher2014-10-141-1/+0
| | | | llvm-svn: 219672
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-2/+2
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+4
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Clean up language and grammar.Eric Christopher2014-05-201-1/+1
| | | | | | | Based on a patch by jfcaron3@gmail.com! PR19806 llvm-svn: 209216
* [Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | | | | | | define below all header includes in the lib/CodeGen/... tree. While the current modules implementation doesn't check for this kind of ODR violation yet, it is likely to grow support for it in the future. It also removes one layer of macro pollution across all the included headers. Other sub-trees will follow. llvm-svn: 206837
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-6/+6
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-071-3/+3
| | | | | | class. llvm-svn: 203220
* Convert register liveness tracking to work on a sub-register level instead ↵Juergen Ributzka2013-12-141-10/+8
| | | | | | | | of just register units. Reviewed by Andy llvm-svn: 197315
* comment typo.Andrew Trick2013-12-131-1/+1
| | | | llvm-svn: 197278
* Revert "Convert liveness tracking to work on a sub-register level instead of ↵Andrew Trick2013-12-131-8/+10
| | | | | | | | | | just register units." This reverts commit r197253. This was a great change, but Juergen should be the commit author. llvm-svn: 197262
* Convert liveness tracking to work on a sub-register level instead of just ↵Andrew Trick2013-12-131-10/+8
| | | | | | register units. llvm-svn: 197253
* Improve on r192635, ExeDepsFix for avx, and add a test case.Andrew Trick2013-10-151-1/+3
| | | | | | | | | rdar:15221834 False AVX register dependencies cause 5x slowdown on flops-5/6 and significant slowdown on several others. This was blocking the switch to MI-Sched. llvm-svn: 192669
* Fix the ExecutionDepsFix pass to handle AVX instructions.Andrew Trick2013-10-141-22/+93
| | | | | | | | | | | | | | | | | | | | | | | | This pass is needed to break false dependencies. Without it, unlucky register assignment can result in wild (5x) swings in performance. This pass was trying to handle AVX but not getting it right. AVX doesn't have partial register defs, it has unused register reads in which the high bits of a source operand are copied into the unused bits of the dest. Fixing this requires conservative liveness analysis. This is awkard because the pass already has its own pseudo-liveness. However, proper liveness is expensive, and we would like to use a generic utility to compute it. The fix only invokes liveness on-demand. It is rare to detect a case that needs undef-read dependence breaking, but when it happens, it can be needed many times within a very large block. I think the existing heuristic which uses a register window of 16 is too conservative for loop-carried false dependencies. If the loop is a reduction. The out-of-order engine may be able to execute several loop iterations in parallel. However, I'll leave this tuning exercise for next time. llvm-svn: 192635
* Use SmallVectorImpl instead of SmallVector for iterators and references to ↵Craig Topper2013-07-031-3/+3
| | | | | | avoid specifying the vector size unnecessarily. llvm-svn: 185512
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-241-2/+2
| | | | llvm-svn: 182680
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-4/+4
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed().Jakob Stoklund Olesen2012-10-171-1/+1
| | | | | | | | | | | All callers of these functions really want the isPhysRegOrOverlapUsed() functionality which also checks aliases. For historical reasons, targets without register aliases were calling isPhysRegUsed() instead. Change isPhysRegUsed() to also check aliases, and switch all isPhysRegOrOverlapUsed() callers to isPhysRegUsed(). llvm-svn: 166117
* Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to ↵Silviu Baranga2012-10-031-3/+6
| | | | | | not propagate through implicit defs. llvm-svn: 165102
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-1/+1
| | | | llvm-svn: 157885
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-1/+2
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
| | | | llvm-svn: 152001
* Move common code into an MRI function.Jakob Stoklund Olesen2011-12-211-5/+4
| | | | llvm-svn: 147071
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Fix PR11422.Jakob Stoklund Olesen2011-11-231-2/+6
| | | | | | | | | | | | | This was a bug in keeping track of the available domains when merging domain values. The wrong domain mask caused ExecutionDepsFix to try to move VANDPSYrr to the integer domain which is only available in AVX2. Also add an assertion to catch future attempts at emitting AVX2 instructions. llvm-svn: 145096
* Check all overlaps when looking for used registers.Jakob Stoklund Olesen2011-11-151-4/+5
| | | | | | A function using any RC alias is enough to enable the ExeDepsFix pass. llvm-svn: 144636
* Break false dependencies before partial register updates.Jakob Stoklund Olesen2011-11-151-0/+27
| | | | | | | | | | | | | | Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix about instructions with partial register updates causing false unwanted dependencies. The ExecutionDepsFix pass will break the false dependencies if the updated register was written in the previoius N instructions. The small loop added to sse-domains.ll runs twice as fast with dependency-breaking instructions inserted. llvm-svn: 144602
* Track register ages more accurately.Jakob Stoklund Olesen2011-11-151-101/+184
| | | | | | | | | | | | | | | Keep track of the last instruction to define each register individually instead of per DomainValue. This lets us track more accurately when a register was last written. Also track register ages across basic blocks. When entering a new basic block, use the least stale predecessor def as a worst case estimate for register age. The register age is used to arbitrate between conflicting domains. The most recently defined register wins. llvm-svn: 144601
* Collapse DomainValues across loop back-edges.Jakob Stoklund Olesen2011-11-091-8/+35
| | | | | | | | | | | | | | During the initial RPO traversal of the basic blocks, remember the ones that are incomplete because of back-edges from predecessors that haven't been visited yet. After the initial RPO, revisit all those loop headers so the incoming DomainValues on the back-edges can be properly collapsed. This will properly fix execution domains on software pipelined code, like the included test case. llvm-svn: 144151
* Link to the live DomainValue after merging.Jakob Stoklund Olesen2011-11-091-13/+50
| | | | | | | | | | | | | | | | When merging two uncollapsed DomainValues, place a link to the active DomainValue from the passive DomainValue. This allows old stale references to the passive DomainValue to be updated to point to the active DomainValue. The new resolve() function finds the active DomainValue and updates the pointer. This change makes old live-out lists more useful since they may contain uncollapsed DomainValues that have since been merged into other DomainValues. llvm-svn: 144149
OpenPOWER on IntegriCloud