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path: root/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
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* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-221-2/+2
| | | | llvm-svn: 182531
* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-051-9/+0
| | | | | | | Now that return value registers are return instruction uses, there is no need for special treatment of return blocks. llvm-svn: 174416
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-151-6/+2
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. llvm-svn: 165983
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-3/+2
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Switch some getAliasSet clients to MCRegAliasIterator.Jakob Stoklund Olesen2012-06-011-4/+2
| | | | | | | MCRegAliasIterator can optionally visit the register itself, allowing for simpler code. llvm-svn: 157837
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-1/+1
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
| | | | llvm-svn: 152001
* Never delete instructions that define reserved registers.Jakob Stoklund Olesen2012-02-091-6/+10
| | | | | | | | | | | I think this was already the intention, but DeadMachineInstructionElim was accidentally tracking the liveness of reserved registers. Now, instructions with reserved defs are never deleted. This prevents the call stack adjustment instructions from getting deleted when enabling register masks. llvm-svn: 150116
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-081-4/+1
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* whitespaceAndrew Trick2012-02-081-1/+1
| | | | llvm-svn: 150094
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-021-4/+1
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. llvm-svn: 149646
* Handle register masks in DeadMachineInstructionElim.Jakob Stoklund Olesen2012-01-201-0/+7
| | | | | | Don't track live physregs that are clobbered by a register mask operand. llvm-svn: 148588
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Track live-out physical registers in MachineDCE.Jakob Stoklund Olesen2011-06-271-3/+8
| | | | | | Patch by Sanjoy Das! llvm-svn: 133910
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-2/+2
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-0/+6
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson2010-10-191-1/+3
| | | | | | | | | | | | | | | | | exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. llvm-svn: 116820
* Now with fewer extraneous semicolons!Owen Anderson2010-10-071-1/+1
| | | | llvm-svn: 115996
* Track liveness of unallocatable, unreserved registers in machine DCE.Jakob Stoklund Olesen2010-08-311-6/+8
| | | | | | | | | | | | | Reserved registers are unpredictable, and are treated as always live by machine DCE. Allocatable registers are never reserved, and can be used for virtual registers. Unreserved, unallocatable registers can not be used for virtual registers, but otherwise behave like a normal allocatable register. Most targets only have the flag register in this set. llvm-svn: 112649
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Fix batch of converting RegisterPass<> to INTIALIZE_PASS().Owen Anderson2010-07-211-3/+2
| | | | llvm-svn: 109045
* Swap parameters of isSafeToMove and isSafeToReMat for consistency.Evan Cheng2010-03-021-1/+1
| | | | llvm-svn: 97578
* Rewrite handling of DBG_VALUE; previous algorithmDale Johannesen2010-02-121-16/+24
| | | | | | | | | | | didn't handle X = Y<dead> = use X DBG_VALUE(X) I was hoping to avoid this approach as it's slower, but I don't think it can be done. llvm-svn: 95996
* Allow for more than one DBG_VALUE targeting theDale Johannesen2010-02-111-4/+4
| | | | | | same dead instruction. llvm-svn: 95890
* Delete dead PHI machine instructions. These can be created due to typeBob Wilson2010-02-101-1/+1
| | | | | | | | | legalization even when the IR-level optimizer has removed dead phis, such as when the high half of an i64 value is unused on a 32-bit target. I had to adjust a few test cases that had dead phis. This is a partial fix for Radar 7627077. llvm-svn: 95816
* more comment updatesDale Johannesen2010-02-101-2/+2
| | | | llvm-svn: 95736
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-1/+1
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* Run codegen dce pass for all targets at all optimization levels. Previously it'sEvan Cheng2010-02-061-0/+5
| | | | | | | | | | only run for x86 with fastisel. I've found it being very effective in eliminating some obvious dead code as result of formal parameter lowering especially when tail call optimization eliminated the need for some of the loads from fixed frame objects. It also shrinks a number of the tests. A couple of tests no longer make sense and are now eliminated. llvm-svn: 95493
* If the only use of something is a DEBUG_VALUE, don'tDale Johannesen2010-01-271-0/+14
| | | | | | | let that stop it from being deleted, and change the DEBUG_VALUE value to undef. llvm-svn: 94694
* Change errs() to dbgs().David Greene2010-01-041-1/+1
| | | | llvm-svn: 92496
* Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky2009-10-251-1/+0
| | | | | | VISIBILITY_HIDDEN removal. llvm-svn: 85043
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-2/+1
| | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. llvm-svn: 85042
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-091-1/+1
| | | | | | | | | | | | | | is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. llvm-svn: 83687
* Convert DOUT to DEBUG(errs()...).Bill Wendling2009-08-221-1/+2
| | | | llvm-svn: 79748
* Add const qualifiers.Dan Gohman2009-08-111-2/+2
| | | | llvm-svn: 78663
* Rename AliasSet to SubRegs, to reflect changes in the surrounding code.Dan Gohman2008-10-161-3/+3
| | | | llvm-svn: 57618
* Fix a subtle bug in DeadMachineInstructionElim's livenessDan Gohman2008-10-161-1/+4
| | | | | | | computation. A def of a register doesn't necessarily kill live super-registers. llvm-svn: 57614
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-3/+3
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Add debug output to this pass.Dan Gohman2008-09-251-0/+2
| | | | llvm-svn: 56602
* Refactor the logic for testing if an instruction is dead into aDan Gohman2008-09-241-37/+48
| | | | | | separate method. llvm-svn: 56531
* Set SetStore to false, to allow this pass to deleteDan Gohman2008-09-241-1/+2
| | | | | | dead loads. llvm-svn: 56529
* Now that DeadMachineInstructionElim is basically workingDan Gohman2008-09-231-6/+0
| | | | | | | correctly, it's not necessary to explicitly remove registers from their use-def lists. llvm-svn: 56509
* Track local physical register liveness. This is not the mostDan Gohman2008-09-231-3/+53
| | | | | | | efficient implementation possible, but it's pretty simple and good enough for the time being. llvm-svn: 56504
* Don't consider instructions with implicit physical registerDan Gohman2008-09-181-1/+2
| | | | | | defs to be necessarily live. llvm-svn: 56310
* Add a new MachineInstr-level DCE pass. It is very simple, and is intended toDan Gohman2008-09-171-0/+99
be used with fast-isel. llvm-svn: 56268
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