| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 55779
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handled correctly, and change a few SmallVector uses to use
size 0 to more clearly reflect their intent.
llvm-svn: 55181
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had to be propoagated down into all the targets and up into all clients of this API.
llvm-svn: 54802
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to be marked invalid regardless of whether it is
a debug, an exception handling or (hopefully) a
GC label.
llvm-svn: 54172
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MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
llvm-svn: 53212
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predessors of exit blocks from tail merging
consideration.
llvm-svn: 52985
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the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
llvm-svn: 52943
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llvm-svn: 52495
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elements that have been erased. Based on a patch
by Nicolas Capens.
llvm-svn: 51485
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several things that were neither in an anonymous namespace nor static
but not intended to be global.
llvm-svn: 51017
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if those blocks consist entirely of common instructions;
merging will not add an extra branch in this case.
llvm-svn: 51006
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semantically identical, but little difference in
either results or execution speed; but it's much
easier to read, at least IMO.
llvm-svn: 50999
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no functional change.
llvm-svn: 50921
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case where there are multiple blocks with a large
number of common tail instructions more efficiently
(compile time optimization).
llvm-svn: 50916
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llvm-svn: 50696
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can't just eliminate them since register scavenger expects every register use to be defined. However, we can delete them when there are no intra-block uses. Carefully removing some implicit def's which enable more blocks to be optimized away.
llvm-svn: 49461
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16-byte boundaries.
llvm-svn: 47703
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order to save a single instruction since a branch will be inserted for each BB.
llvm-svn: 47301
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llvm-svn: 46930
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llvm-svn: 46514
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Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
llvm-svn: 45695
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that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
llvm-svn: 45674
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llvm-svn: 45667
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llvm-svn: 45656
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e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
llvm-svn: 45464
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llvm-svn: 45418
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impact the value of fall-through choices.
llvm-svn: 44785
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llvm-svn: 43359
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llvm-svn: 43353
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llvm-svn: 43191
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llvm-svn: 40757
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llvm-svn: 38535
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llvm-svn: 38516
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_GLIBCXX_DEBUG.
llvm-svn: 37793
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method.
llvm-svn: 37633
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llvm-svn: 37511
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is too slow.
llvm-svn: 37509
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llvm-svn: 37427
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general facility.
llvm-svn: 37408
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llvm-svn: 37394
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See test/CodeGen/X86/test-pic-jtbl.ll for a case where it works well;
shaves another 10K off our favorite benchmark. I was hesitant about
this because of compile speed, but seems to do OK on a bootstrap.
llvm-svn: 37392
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Do not remove empty landing pads (EH table needs to be updated)
llvm-svn: 37375
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llvm-svn: 37355
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matter until my last change). Reenable tail merging by default.
llvm-svn: 37354
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only one successor.
llvm-svn: 37324
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Temporarily, this breaks CodeGen/Generic/2006-02-12-InsertLibraryCall.ll
by exposing an unrelated latent problem; working on that.
llvm-svn: 37323
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When considering blocks with more than 2 predecessors, merge the block with
the largest number of matching insns, rather than the first block found.
Considering that 1 matching insn is enough to show a win for candidates that
already end with a branch.
llvm-svn: 37315
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for a target-dependent default with a command-line override; this way
should be generally usable.
llvm-svn: 37285
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llvm-svn: 37198
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llvm-svn: 37089
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