| Commit message (Collapse) | Author | Age | Files | Lines |
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sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
llvm-svn: 134021
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llvm-svn: 132995
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llvm-svn: 132988
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sharp all or nothing transition when one extra predecessor was added. Now
we still test first ones for merging.
llvm-svn: 132974
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llvm-svn: 132149
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llvm-svn: 132148
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llvm-svn: 131258
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test bug and also taught it to update liveins.
llvm-svn: 131241
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configuration.
llvm-svn: 131235
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markers. In some cases a register def is dead on one path, but not on
another.
This is passing Clang self-hosting.
llvm-svn: 131214
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to provide a reduced testcase.
llvm-svn: 131176
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at the start of basic blocks to their common predecessor. It's actually quite
common (e.g. about 50 times in JM/lencod) and has shown to be a nice code size
benefit. e.g.
pushq %rax
testl %edi, %edi
jne LBB0_2
## BB#1:
xorb %al, %al
popq %rdx
ret
LBB0_2:
xorb %al, %al
callq _foo
popq %rdx
ret
=>
pushq %rax
xorb %al, %al
testl %edi, %edi
je LBB0_2
## BB#1:
callq _foo
LBB0_2:
popq %rdx
ret
rdar://9145558
llvm-svn: 131172
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An exception is thrown via a call to _cxa_throw, which we don't expect to
return. Therefore, the "true" part of the invoke goes to a BB that has
'unreachable' as its only instruction. This is lowered into an empty MachineBB.
The landing pad for this invoke, however, is directly after the "true" MBB.
When the empty MBB is removed, the landing pad is directly below the BB with the
invoke call. The unconditional branch is removed and then the two blocks are
merged together.
The testcase is too big for a regression test.
<rdar://problem/9305728>
llvm-svn: 129965
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llvm-svn: 126158
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llvm-svn: 110460
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llvm-svn: 110410
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address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
llvm-svn: 110396
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llvm-svn: 106517
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- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
llvm-svn: 106344
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addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
llvm-svn: 106243
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beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.
The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.
Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.
And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.
llvm-svn: 102907
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folder to be tolerant of debug info following the
branch(es) at the end of a block.
llvm-svn: 100168
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disabled for several months (since svn r88806) and no one noticed. My fix
for pr6543 yesterday reenabled it, but broke the ARM port's code for using
TBB/TBH. Rather than adding a target hook to disable merging for Thumb2 only,
I'm just taking this out. It is not common to have identical jump tables,
the code we used to merge them was O(N^2), and it only helps code size, not
performance.
llvm-svn: 98977
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llvm-svn: 98694
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them with a counter.
llvm-svn: 98462
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llvm-svn: 98181
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llvm-svn: 98137
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llvm-svn: 98108
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llvm-svn: 98104
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llvm-svn: 97938
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llvm-svn: 97765
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into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
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1. MachineJumpTableInfo is now created lazily for a function the first time
it actually makes a jump table instead of for every function.
2. The encoding of jump table entries is now described by the
MachineJumpTableInfo::JTEntryKind enum. This enum is determined by the
TLI::getJumpTableEncoding() hook, instead of by lots of code scattered
throughout the compiler that "knows" that jump table entries are always
32-bits in pic mode (for example).
3. The size and alignment of jump table entries is now calculated based on
their kind, instead of at machinefunction creation time.
Future work includes using the EntryKind in more places in the compiler,
eliminating other logic that "knows" the layout of jump tables in various
situations.
llvm-svn: 94470
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llvm-svn: 92097
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llvm-svn: 91477
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llvm-svn: 91475
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$ svn merge -c -91161 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91161 into '.':
U lib/CodeGen/BranchFolding.cpp
U lib/CodeGen/MachineBasicBlock.cpp
$ svn merge -c -91113 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91113 into '.':
G lib/CodeGen/MachineBasicBlock.cpp
$ svn merge -c -91101 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91101 into '.':
U include/llvm/CodeGen/MachineBasicBlock.h
G lib/CodeGen/MachineBasicBlock.cpp
$ svn merge -c -91092 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91092 into '.':
G include/llvm/CodeGen/MachineBasicBlock.h
G lib/CodeGen/MachineBasicBlock.cpp
llvm-svn: 91376
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branches only to a landing pad. Without this check, the compiler would go into
an infinite loop because the branch to a landing pad is an "abnormal" edge which
wasn't being taken into account.
This is the meat of that fix:
if (!PrevBB.canFallThrough() && !MBB->BranchesToLandingPad(MBB)) {
The other stuff is simplification of the "branches to a landing pad" code.
llvm-svn: 91161
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MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
llvm-svn: 90634
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Patch by Howard Hinnant!
llvm-svn: 90365
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running tail duplication when doing branch folding for if-conversion, and
we also want to be able to run tail duplication earlier to fix some
reg alloc problems. Move the CanFallThrough function from BranchFolding
to MachineBasicBlock so that it can be shared by TailDuplication.
llvm-svn: 89904
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Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation. I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size. ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.
llvm-svn: 89814
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llvm-svn: 89275
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the tail of a block may make that block a new candidate for duplication.
llvm-svn: 89264
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llvm-svn: 89254
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llvm-svn: 89225
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contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.
llvm-svn: 89187
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unnecessary. It is broken because the "isIdenticalTo" check should be
negated. If that is fixed, this code causes the CodeGen/X86/tail-opts.ll
test to fail, in the dont_merge_oddly function. And, I confirmed that the
regression is real -- the generated code is worse. As far as I can tell,
that tail-opts.ll test is checking for what this code is supposed to handle
and we're doing the right thing anyway.
llvm-svn: 89121
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llvm-svn: 89114
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folding optimizations.
llvm-svn: 89109
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